[all-commits] [llvm/llvm-project] d04ae1: [AArch64] Use DAG->isAddLike in add_and_or_is_add ...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d04ae1b15ff3064e9fb43a3a15f43285d4ee7998
      https://github.com/llvm/llvm-project/commit/d04ae1b15ff3064e9fb43a3a15f43285d4ee7998
  Author: David Green <david.green at arm.com>
  Date:   2024-01-31 (Wed, 31 Jan 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-csel.ll
    M llvm/test/CodeGen/AArch64/shift-accumulate.ll

  Log Message:
  -----------
  [AArch64] Use DAG->isAddLike in add_and_or_is_add (#79563)

This allows it to work with disjoint or's as well as computing the known
bits.