[all-commits] [llvm/llvm-project] cfd0dc: [𝘀𝗽𝗿] initial version

[Alexey Bataev via All-commits]

  Branch: refs/heads/users/alexey-bataev/spr/ttiriscvimprove-costs-for-fixed-vector-whole-reg-extractinsert
  Home:   https://github.com/llvm/llvm-project
  Commit: cfd0dcfa1f5fabd12cf4d7bf8d5a10bd324ace0a
      https://github.com/llvm/llvm-project/commit/cfd0dcfa1f5fabd12cf4d7bf8d5a10bd324ace0a
  Author: Alexey Bataev <a.bataev at outlook.com>
  Date:   2024-01-31 (Wed, 31 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/RISCV/shuffle-extract_subvector.ll
    M llvm/test/Analysis/CostModel/RISCV/shuffle-insert_subvector.ll
    M llvm/test/Analysis/CostModel/RISCV/shuffle-interleave.ll

  Log Message:
  -----------
  [𝘀𝗽𝗿] initial version

Created using spr 1.3.5