[all-commits] [llvm/llvm-project] c92ad4: Recommit "[RISCV] Support __riscv_v_fixed_vlen for...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c92ad411f2f94d8521cd18abcb37285f9a390ecb
      https://github.com/llvm/llvm-project/commit/c92ad411f2f94d8521cd18abcb37285f9a390ecb
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-01-25 (Thu, 25 Jan 2024)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/include/clang/AST/Type.h
    M clang/include/clang/Basic/AttrDocs.td
    M clang/lib/AST/ASTContext.cpp
    M clang/lib/AST/ItaniumMangle.cpp
    M clang/lib/AST/JSONNodeDumper.cpp
    M clang/lib/AST/TextNodeDumper.cpp
    M clang/lib/AST/Type.cpp
    M clang/lib/AST/TypePrinter.cpp
    M clang/lib/CodeGen/Targets/RISCV.cpp
    M clang/lib/Sema/SemaExpr.cpp
    M clang/lib/Sema/SemaType.cpp
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-bitcast.c
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-cast.c
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-globals.c
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-types.c
    M clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
    M clang/test/Sema/attr-riscv-rvv-vector-bits.c

  Log Message:
  -----------
  Recommit "[RISCV] Support __riscv_v_fixed_vlen for vbool types. (#76551)"

Test updated to expect i8 gep.

Original message:

This adopts a similar behavior to AArch64 SVE, where bool vectors are
represented as a vector of chars with 1/8 the number of elements. This
ensures the vector always occupies a power of 2 number of bytes.

A consequence of this is that vbool64_t, vbool32_t, and vool16_t can
only be used with a vector length that guarantees at least 8 bits.