[all-commits] [llvm/llvm-project] b856e7: Set MaxAtomicSizeInBitsSupported for remaining tar...

[James Y Knight via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b856e77b2df212d740bfedc984572d812d07ecc8
      https://github.com/llvm/llvm-project/commit/b856e77b2df212d740bfedc984572d812d07ecc8
  Author: James Y Knight <jyknight at google.com>
  Date:   2024-01-08 (Mon, 08 Jan 2024)

  Changed paths:
    M llvm/lib/Target/ARC/ARCISelLowering.cpp
    M llvm/lib/Target/ARC/ARCTargetMachine.cpp
    M llvm/lib/Target/BPF/BPFISelLowering.cpp
    M llvm/lib/Target/BPF/BPFTargetMachine.cpp
    M llvm/lib/Target/Lanai/LanaiISelLowering.cpp
    M llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
    M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
    M llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    A llvm/test/CodeGen/ARC/atomic-oversize.ll
    A llvm/test/CodeGen/BPF/atomic-oversize.ll
    A llvm/test/CodeGen/Lanai/atomic-oversize.ll
    A llvm/test/CodeGen/MSP430/atomic-oversize.ll
    M llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll

  Log Message:
  -----------
  Set MaxAtomicSizeInBitsSupported for remaining targets. (#75703)

Targets affected:

- NVPTX and BPF: set to 64 bits.
- ARC, Lanai, and MSP430: set to 0 (they don't implement atomics).

Those which didn't yet add AtomicExpandPass to their pass pipeline now
do so.

This will result in larger atomic operations getting expanded to
`__atomic_*` libcalls via AtomicExpandPass. On all these targets, this
now matches what Clang already does in the frontend.

The only targets which do not configure AtomicExpandPass now are:
- DirectX and SPIRV: they aren't normal backends.
- AVR: a single-cpu architecture with no privileged/user divide, which
could implement all atomics by disabling/enabling interrupts, regardless
of size/alignment. Will be addressed by future work.