[all-commits] [llvm/llvm-project] 96c4f1: [RISCV] Add support predicating for ANDN/ORN/XNOR ...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 96c4f1034cc3a93dafa9f8541548249deb813b78
      https://github.com/llvm/llvm-project/commit/96c4f1034cc3a93dafa9f8541548249deb813b78
  Author: Jim Lin <jim at andestech.com>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll

  Log Message:
  -----------
  [RISCV] Add support predicating for ANDN/ORN/XNOR with short-forward-branch-opt. (#77077)

ANDN/ORN/XNOR are like other ALU instructions. It should be able to be
predicated by the cpu that supports short-forward-branch.