[all-commits] [llvm/llvm-project] 7d0e46: [𝘀𝗽𝗿] initial version

[Fangrui Song via All-commits]

  Branch: refs/heads/users/MaskRay/spr/riscv-merge-machine-operand-flag-mo_plt-into-mo_call
  Home:   https://github.com/llvm/llvm-project
  Commit: 7d0e46b06b082cb41efab85d179891aa8baac6be
      https://github.com/llvm/llvm-project/commit/7d0e46b06b082cb41efab85d179891aa8baac6be
  Author: Fangrui Song <i at maskray.me>
  Date:   2024-01-07 (Sun, 07 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/variadic-call.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ceil-floor.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir
    M llvm/test/CodeGen/RISCV/float-select-verify.ll
    M llvm/test/CodeGen/RISCV/live-sp.mir
    M llvm/test/CodeGen/RISCV/make-compressible.mir
    M llvm/test/CodeGen/RISCV/mir-target-flags.ll
    M llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
    M llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
    M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
    M llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
    M llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
    M llvm/test/CodeGen/RISCV/vector-abi.ll

  Log Message:
  -----------
  [𝘀𝗽𝗿] initial version

Created using spr 1.3.4