[all-commits] [llvm/llvm-project] eabaee: [RISCV] Omit "@plt" in assembly output "call foo at p...

Fangrui Song via All-commits all-commits at lists.llvm.org
Sun Jan 7 12:09:57 PST 2024 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: eabaee0c59110d0e11b33a69db54ccda526b35fd
      https://github.com/llvm/llvm-project/commit/eabaee0c59110d0e11b33a69db54ccda526b35fd
  Author: Fangrui Song <i at maskray.me>
  Date:   2024-01-07 (Sun, 07 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
    M llvm/test/CodeGen/RISCV/addrspacecast.ll
    M llvm/test/CodeGen/RISCV/aext-to-sext.ll
    M llvm/test/CodeGen/RISCV/alloca.ll
    M llvm/test/CodeGen/RISCV/analyze-branch.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
    M llvm/test/CodeGen/RISCV/atomic-load-store.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/atomic-signext.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/RISCV/bf16-promote.ll
    M llvm/test/CodeGen/RISCV/bfloat-br-fcmp.ll
    M llvm/test/CodeGen/RISCV/bfloat-convert.ll
    M llvm/test/CodeGen/RISCV/bfloat-frem.ll
    M llvm/test/CodeGen/RISCV/bfloat-mem.ll
    M llvm/test/CodeGen/RISCV/bfloat.ll
    M llvm/test/CodeGen/RISCV/bittest.ll
    M llvm/test/CodeGen/RISCV/byval.ll
    M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
    M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
    M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
    M llvm/test/CodeGen/RISCV/calling-conv-half.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
    M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
    M llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
    M llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll
    M llvm/test/CodeGen/RISCV/calls.ll
    M llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll
    M llvm/test/CodeGen/RISCV/condops.ll
    M llvm/test/CodeGen/RISCV/copysign-casts.ll
    M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
    M llvm/test/CodeGen/RISCV/div-by-constant.ll
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/double-arith-strict.ll
    M llvm/test/CodeGen/RISCV/double-arith.ll
    M llvm/test/CodeGen/RISCV/double-br-fcmp.ll
    M llvm/test/CodeGen/RISCV/double-calling-conv.ll
    M llvm/test/CodeGen/RISCV/double-convert-strict.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
    M llvm/test/CodeGen/RISCV/double-fcmp.ll
    M llvm/test/CodeGen/RISCV/double-frem.ll
    M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
    M llvm/test/CodeGen/RISCV/double-intrinsics.ll
    M llvm/test/CodeGen/RISCV/double-mem.ll
    M llvm/test/CodeGen/RISCV/double-previous-failure.ll
    M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/double-round-conv.ll
    M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
    M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
    M llvm/test/CodeGen/RISCV/emutls.ll
    M llvm/test/CodeGen/RISCV/exception-pointer-register.ll
    M llvm/test/CodeGen/RISCV/fastcc-float.ll
    M llvm/test/CodeGen/RISCV/fastcc-int.ll
    M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
    M llvm/test/CodeGen/RISCV/fli-licm.ll
    M llvm/test/CodeGen/RISCV/float-arith-strict.ll
    M llvm/test/CodeGen/RISCV/float-arith.ll
    M llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
    M llvm/test/CodeGen/RISCV/float-br-fcmp.ll
    M llvm/test/CodeGen/RISCV/float-convert-strict.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
    M llvm/test/CodeGen/RISCV/float-fcmp.ll
    M llvm/test/CodeGen/RISCV/float-frem.ll
    M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
    M llvm/test/CodeGen/RISCV/float-intrinsics.ll
    M llvm/test/CodeGen/RISCV/float-mem.ll
    M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/float-round-conv.ll
    M llvm/test/CodeGen/RISCV/float-zfa.ll
    M llvm/test/CodeGen/RISCV/fmax-fmin.ll
    M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
    M llvm/test/CodeGen/RISCV/forced-atomics.ll
    M llvm/test/CodeGen/RISCV/fp128.ll
    M llvm/test/CodeGen/RISCV/fp16-promote.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/frame-info.ll
    M llvm/test/CodeGen/RISCV/frame.ll
    M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
    M llvm/test/CodeGen/RISCV/ghccc-rv32.ll
    M llvm/test/CodeGen/RISCV/ghccc-rv64.ll
    M llvm/test/CodeGen/RISCV/ghccc-without-f-reg.ll
    M llvm/test/CodeGen/RISCV/half-arith.ll
    M llvm/test/CodeGen/RISCV/half-br-fcmp.ll
    M llvm/test/CodeGen/RISCV/half-convert-strict.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-frem.ll
    M llvm/test/CodeGen/RISCV/half-intrinsics.ll
    M llvm/test/CodeGen/RISCV/half-mem.ll
    M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/half-round-conv.ll
    M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr.ll
    M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
    M llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
    M llvm/test/CodeGen/RISCV/llvm.exp10.ll
    M llvm/test/CodeGen/RISCV/llvm.frexp.ll
    M llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll
    M llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
    M llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
    M llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
    M llvm/test/CodeGen/RISCV/mem.ll
    M llvm/test/CodeGen/RISCV/mem64.ll
    M llvm/test/CodeGen/RISCV/memcpy.ll
    M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
    M llvm/test/CodeGen/RISCV/mul.ll
    M llvm/test/CodeGen/RISCV/nest-register.ll
    M llvm/test/CodeGen/RISCV/nomerge.ll
    M llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
    M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
    M llvm/test/CodeGen/RISCV/pr51206.ll
    M llvm/test/CodeGen/RISCV/pr63816.ll
    M llvm/test/CodeGen/RISCV/push-pop-popret.ll
    M llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll
    M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
    M llvm/test/CodeGen/RISCV/rem.ll
    M llvm/test/CodeGen/RISCV/remat.ll
    M llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
    M llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
    M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/rv64-large-stack.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/mem64.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
    M llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
    M llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
    M llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
    M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbs.ll
    M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
    M llvm/test/CodeGen/RISCV/rvv/localvar.ll
    M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
    M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
    M llvm/test/CodeGen/RISCV/rvv/pr63596.ll
    M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
    M llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
    M llvm/test/CodeGen/RISCV/select-and.ll
    M llvm/test/CodeGen/RISCV/select-cc.ll
    M llvm/test/CodeGen/RISCV/select-or.ll
    M llvm/test/CodeGen/RISCV/setcc-logic.ll
    M llvm/test/CodeGen/RISCV/sextw-removal.ll
    M llvm/test/CodeGen/RISCV/shadowcallstack.ll
    M llvm/test/CodeGen/RISCV/shifts.ll
    M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
    M llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll
    M llvm/test/CodeGen/RISCV/shrinkwrap.ll
    M llvm/test/CodeGen/RISCV/split-sp-adjust.ll
    M llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
    M llvm/test/CodeGen/RISCV/split-urem-by-constant.ll
    M llvm/test/CodeGen/RISCV/srem-lkk.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/stack-protector-target.ll
    M llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
    M llvm/test/CodeGen/RISCV/stack-realignment.ll
    M llvm/test/CodeGen/RISCV/stack-slot-size.ll
    M llvm/test/CodeGen/RISCV/stack-store-check.ll
    M llvm/test/CodeGen/RISCV/tls-models.ll
    M llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll
    M llvm/test/CodeGen/RISCV/urem-lkk.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/vararg.ll
    M llvm/test/CodeGen/RISCV/vlenb.ll
    M llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll
    M llvm/test/CodeGen/RISCV/zcmp-with-float.ll
    M llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
    M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
    M llvm/test/MC/RISCV/function-call.s
    M llvm/test/MC/RISCV/tail-call.s

  Log Message:
  -----------
  [RISCV] Omit "@plt" in assembly output "call foo at plt" (#72467)

R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and
R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530
`call foo` assembles to R_RISCV_CALL_PLT. The `@plt` suffix is not
useful and can be removed now (matching AArch64 and PowerPC).

GNU assembler assembles `call foo` to RISCV_CALL_PLT since 2022-09
(70f35d72ef04cd23771875c1661c9975044a749c).

Without this patch, unconditionally changing MO_CALL to MO_PLT could
create `jump .L1 at plt, a0`, which is invalid in LLVM integrated assembler
and GNU assembler.

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