[all-commits] [llvm/llvm-project] 90f816: [RISCV] Rename TuneVeyronFusions to TuneVentanaVeyron

[Wang Pengcheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 90f816e61f48c22861aeadf31ca6338f88f9e08a
      https://github.com/llvm/llvm-project/commit/90f816e61f48c22861aeadf31ca6338f88f9e08a
  Author: wangpc <wangpengcheng.pp at bytedance.com>
  Date:   2023-12-22 (Fri, 22 Dec 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Rename TuneVeyronFusions to TuneVentanaVeyron

And fusion features are added to processor definition.