[all-commits] [llvm/llvm-project] b83b28: [RISCV] Make Zhinx and Zvfh imply Zhinxmin and Zvf...

[Yeting Kuo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b83b28779ee56236aaf8827398f889334abbd28d
      https://github.com/llvm/llvm-project/commit/b83b28779ee56236aaf8827398f889334abbd28d
  Author: Yeting Kuo <46629943+yetingk at users.noreply.github.com>
  Date:   2023-12-18 (Mon, 18 Dec 2023)

  Changed paths:
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch.s

  Log Message:
  -----------
  [RISCV] Make Zhinx and Zvfh imply Zhinxmin and Zvfhmin respectively (#75735)

Zhinxmin is a subset of Zhinx and Zvfhmin is also a subset of Zvfh.