[all-commits] [llvm/llvm-project] dbe9a6: [RISCV] Correct the VLOperand for masked vssrl/vss...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dbe9a602561d5eecfc1652aab7e127754cb963c0
      https://github.com/llvm/llvm-project/commit/dbe9a602561d5eecfc1652aab7e127754cb963c0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-12-17 (Sun, 17 Dec 2023)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td

  Log Message:
  -----------
  [RISCV] Correct the VLOperand for masked vssrl/vssra intrinsics.

Though I can't prove it matters for anything. The only use of
VLOperand I know of is for handling i64 splat operands to .vx
intrinsics on RV32. Shifts are special and always use XLen for .vx
so they are always legal.