[all-commits] [llvm/llvm-project] e8a15e: [RISCV] Prefer whole register loads and stores whe...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e8a15eca92f1a10b3af4f4e52f54d9d2d7612bf5
      https://github.com/llvm/llvm-project/commit/e8a15eca92f1a10b3af4f4e52f54d9d2d7612bf5
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-12-15 (Fri, 15 Dec 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

  Log Message:
  -----------
  [RISCV] Prefer whole register loads and stores when VL=VLMAX (#75531)

If we're lowering a fixed length vector load or store which happens to
exactly VLEN in size (when VLEN is exactly known), we can use a whole
register load or store instead of the unit strided variants. This
doesn't require a vsetvli in some cases, allows additional flexibility
of vsetvli cases in others, and doesn't have a runtime dependency on the
value of VL.