[all-commits] [llvm/llvm-project] a65ccc: [SystemZ] Support i128 as legal type in VRs (#74625)

Ulrich Weigand via All-commits all-commits at lists.llvm.org
Fri Dec 15 03:55:28 PST 2023


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a65ccc1b9fe740c9f65d9cf2b627de50278aad56
      https://github.com/llvm/llvm-project/commit/a65ccc1b9fe740c9f65d9cf2b627de50278aad56
  Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
  Date:   2023-12-15 (Fri, 15 Dec 2023)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsSystemZ.def
    M clang/lib/Headers/vecintrin.h
    M clang/test/CodeGen/SystemZ/builtins-systemz-error2.c
    M clang/test/CodeGen/SystemZ/builtins-systemz-vector.c
    M clang/test/CodeGen/SystemZ/builtins-systemz-vector2-error.c
    M clang/test/CodeGen/SystemZ/builtins-systemz-vector2.c
    M clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
    M clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-error.c
    M clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c
    M llvm/include/llvm/IR/IntrinsicsSystemZ.td
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/Target/SystemZ/SystemZCallingConv.td
    M llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
    M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
    M llvm/lib/Target/SystemZ/SystemZISelLowering.h
    M llvm/lib/Target/SystemZ/SystemZInstrVector.td
    M llvm/lib/Target/SystemZ/SystemZOperands.td
    M llvm/lib/Target/SystemZ/SystemZOperators.td
    M llvm/lib/Target/SystemZ/SystemZRegisterInfo.td
    A llvm/test/CodeGen/SystemZ/and-10.ll
    A llvm/test/CodeGen/SystemZ/and-11.ll
    A llvm/test/CodeGen/SystemZ/args-12.ll
    A llvm/test/CodeGen/SystemZ/args-13.ll
    A llvm/test/CodeGen/SystemZ/asm-21.ll
    M llvm/test/CodeGen/SystemZ/atomic-load-05.ll
    M llvm/test/CodeGen/SystemZ/atomic-store-05.ll
    M llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
    A llvm/test/CodeGen/SystemZ/bswap-09.ll
    A llvm/test/CodeGen/SystemZ/bswap-10.ll
    A llvm/test/CodeGen/SystemZ/call-zos-i128.ll
    M llvm/test/CodeGen/SystemZ/cmpxchg-06.ll
    A llvm/test/CodeGen/SystemZ/ctpop-03.ll
    A llvm/test/CodeGen/SystemZ/ctpop-04.ll
    M llvm/test/CodeGen/SystemZ/fp-conv-19.ll
    A llvm/test/CodeGen/SystemZ/fp-conv-20.ll
    A llvm/test/CodeGen/SystemZ/fp-strict-conv-17.ll
    A llvm/test/CodeGen/SystemZ/int-abs-02.ll
    A llvm/test/CodeGen/SystemZ/int-add-19.ll
    A llvm/test/CodeGen/SystemZ/int-cmp-63.ll
    A llvm/test/CodeGen/SystemZ/int-const-07.ll
    A llvm/test/CodeGen/SystemZ/int-conv-14.ll
    A llvm/test/CodeGen/SystemZ/int-div-07.ll
    A llvm/test/CodeGen/SystemZ/int-max-01.ll
    A llvm/test/CodeGen/SystemZ/int-min-01.ll
    A llvm/test/CodeGen/SystemZ/int-mul-12.ll
    A llvm/test/CodeGen/SystemZ/int-mul-13.ll
    A llvm/test/CodeGen/SystemZ/int-neg-03.ll
    A llvm/test/CodeGen/SystemZ/int-sub-12.ll
    A llvm/test/CodeGen/SystemZ/int-uadd-13.ll
    A llvm/test/CodeGen/SystemZ/int-uadd-14.ll
    A llvm/test/CodeGen/SystemZ/int-usub-12.ll
    A llvm/test/CodeGen/SystemZ/int-usub-13.ll
    A llvm/test/CodeGen/SystemZ/or-09.ll
    A llvm/test/CodeGen/SystemZ/or-10.ll
    M llvm/test/CodeGen/SystemZ/regalloc-GR128.ll
    A llvm/test/CodeGen/SystemZ/rot-03.ll
    A llvm/test/CodeGen/SystemZ/scalar-ctlz-01.ll
    A llvm/test/CodeGen/SystemZ/scalar-ctlz-02.ll
    R llvm/test/CodeGen/SystemZ/scalar-ctlz.ll
    A llvm/test/CodeGen/SystemZ/scalar-cttz-01.ll
    A llvm/test/CodeGen/SystemZ/scalar-cttz-02.ll
    M llvm/test/CodeGen/SystemZ/shift-12.ll
    A llvm/test/CodeGen/SystemZ/shift-13.ll
    A llvm/test/CodeGen/SystemZ/shift-14.ll
    A llvm/test/CodeGen/SystemZ/shift-15.ll
    M llvm/test/CodeGen/SystemZ/store-replicated-vals.ll
    M llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
    M llvm/test/CodeGen/SystemZ/tdc-04.ll
    M llvm/test/CodeGen/SystemZ/vec-intrinsics-01.ll
    M llvm/test/CodeGen/SystemZ/vec-intrinsics-02.ll
    A llvm/test/CodeGen/SystemZ/xor-09.ll
    A llvm/test/CodeGen/SystemZ/xor-10.ll

  Log Message:
  -----------
  [SystemZ] Support i128 as legal type in VRs (#74625)

On processors supporting vector registers and SIMD instructions, enable
i128 as legal type in VRs. This allows many operations to be implemented
via native instructions directly in VRs (including add, subtract,
logical operations and shifts). For a few other operations (e.g.
multiply and divide, as well as atomic operations), we need to move the
i128 value back to a GPR pair to use the corresponding instruction
there. Overall, this is still beneficial.

The patch includes the following LLVM changes:
- Enable i128 as legal type
- Set up legal operations (in SystemZInstrVector.td)
- Custom expansion for i128 add/subtract with carry
- Custom expansion for i128 comparisons and selects
- Support for moving i128 to/from GPR pairs when required
- Handle 128-bit integer constant values everywhere
- Use i128 as intrinsic operand type where appropriate
- Updated and new test cases

In addition, clang builtins are updated to reflect the intrinsic operand
type changes (which also improves compatibility with GCC).




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