[all-commits] [llvm/llvm-project] c532ba: [RISCV] Support printing immediate of RISCV MCInst...
Wang Yaduo via All-commits
all-commits at lists.llvm.org
Thu Dec 14 22:45:05 PST 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: c532ba4edd7ad7675ba450ba43268aa9e7bda46b
https://github.com/llvm/llvm-project/commit/c532ba4edd7ad7675ba450ba43268aa9e7bda46b
Author: Wang Yaduo <wangyaduo at linux.alibaba.com>
Date: 2023-12-14 (Thu, 14 Dec 2023)
Changed paths:
M bolt/test/RISCV/call-annotations.s
M bolt/test/RISCV/relax.s
M bolt/test/RISCV/reloc-tls.s
M bolt/test/RISCV/reorder-blocks-reverse.s
M bolt/test/RISCV/tls-le-gnu-ld.test
M lld/test/ELF/riscv-call.s
M lld/test/ELF/riscv-hi20-lo12.s
M lld/test/ELF/riscv-ifunc-nonpreemptible.s
M lld/test/ELF/riscv-pcrel-hilo.s
M lld/test/ELF/riscv-plt.s
M lld/test/ELF/riscv-relax-align-rvc.s
M lld/test/ELF/riscv-relax-align.s
M lld/test/ELF/riscv-relax-call.s
M lld/test/ELF/riscv-relax-call2.s
M lld/test/ELF/riscv-relax-emit-relocs.s
M lld/test/ELF/riscv-relax-hi20-lo12-pie.s
M lld/test/ELF/riscv-relax-hi20-lo12.s
M lld/test/ELF/riscv-reloc-got.s
M lld/test/ELF/riscv-tls-gd.s
M lld/test/ELF/riscv-tls-ie.s
M lld/test/ELF/riscv-tls-ld.s
M lld/test/ELF/riscv-tls-le.s
M lld/test/ELF/riscv-undefined-weak.s
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/test/CodeGen/RISCV/compress-double.ll
M llvm/test/CodeGen/RISCV/compress-float.ll
M llvm/test/CodeGen/RISCV/compress-opt-branch.ll
M llvm/test/CodeGen/RISCV/compress-opt-select.ll
M llvm/test/CodeGen/RISCV/compress.ll
M llvm/test/CodeGen/RISCV/option-nopic.ll
M llvm/test/CodeGen/RISCV/option-pic.ll
M llvm/test/CodeGen/RISCV/option-rvc.ll
M llvm/test/MC/RISCV/XTHeadBa-valid.s
M llvm/test/MC/RISCV/attribute-with-insts.s
M llvm/test/MC/RISCV/compress-rv32d.s
M llvm/test/MC/RISCV/compress-rv32f.s
M llvm/test/MC/RISCV/compress-rv32i.s
M llvm/test/MC/RISCV/compress-rv64i.s
M llvm/test/MC/RISCV/corev/XCValu-valid.s
M llvm/test/MC/RISCV/corev/XCVbi.s
M llvm/test/MC/RISCV/corev/XCVbitmanip.s
M llvm/test/MC/RISCV/corev/XCVelw-valid.s
M llvm/test/MC/RISCV/corev/XCVmac-valid.s
M llvm/test/MC/RISCV/corev/XCVmem-valid.s
M llvm/test/MC/RISCV/corev/XCVsimd.s
M llvm/test/MC/RISCV/csr-aliases.s
M llvm/test/MC/RISCV/fixups.s
M llvm/test/MC/RISCV/hilo-constaddr.s
M llvm/test/MC/RISCV/insn.s
M llvm/test/MC/RISCV/insn_c.s
M llvm/test/MC/RISCV/nop-slide.s
M llvm/test/MC/RISCV/numeric-reg-names.s
M llvm/test/MC/RISCV/option-arch.s
M llvm/test/MC/RISCV/option-mix.s
M llvm/test/MC/RISCV/option-pushpop.s
M llvm/test/MC/RISCV/option-rvc.s
M llvm/test/MC/RISCV/pcrel-fixups.s
A llvm/test/MC/RISCV/print-imm-hex.s
M llvm/test/MC/RISCV/rv32c-aliases-valid.s
M llvm/test/MC/RISCV/rv32c-only-valid.s
M llvm/test/MC/RISCV/rv32c-valid.s
M llvm/test/MC/RISCV/rv32d-valid.s
M llvm/test/MC/RISCV/rv32dc-valid.s
M llvm/test/MC/RISCV/rv32e-valid.s
M llvm/test/MC/RISCV/rv32f-valid.s
M llvm/test/MC/RISCV/rv32fc-aliases-valid.s
M llvm/test/MC/RISCV/rv32fc-valid.s
M llvm/test/MC/RISCV/rv32i-aliases-valid.s
M llvm/test/MC/RISCV/rv32i-only-valid.s
M llvm/test/MC/RISCV/rv32i-valid.s
M llvm/test/MC/RISCV/rv32xtheadbs-valid.s
M llvm/test/MC/RISCV/rv32xtheadfmemidx-valid.s
M llvm/test/MC/RISCV/rv32zbb-aliases-valid.s
M llvm/test/MC/RISCV/rv32zbb-only-valid.s
M llvm/test/MC/RISCV/rv32zbkb-valid.s
M llvm/test/MC/RISCV/rv32zbs-aliases-valid.s
M llvm/test/MC/RISCV/rv32zbs-valid.s
M llvm/test/MC/RISCV/rv32zcb-valid.s
M llvm/test/MC/RISCV/rv32zcmt-valid.s
M llvm/test/MC/RISCV/rv32zfbfmin-valid.s
M llvm/test/MC/RISCV/rv32zfh-valid.s
M llvm/test/MC/RISCV/rv32zfhmin-valid.s
M llvm/test/MC/RISCV/rv32zicbop-valid.s
M llvm/test/MC/RISCV/rv32zknd-only-valid.s
M llvm/test/MC/RISCV/rv32zkne-only-valid.s
M llvm/test/MC/RISCV/rv32zksed-valid.s
M llvm/test/MC/RISCV/rv64-machine-csr-names.s
M llvm/test/MC/RISCV/rv64-user-csr-names.s
M llvm/test/MC/RISCV/rv64c-aliases-valid.s
M llvm/test/MC/RISCV/rv64c-hints-valid.s
M llvm/test/MC/RISCV/rv64c-valid.s
M llvm/test/MC/RISCV/rv64dc-valid.s
M llvm/test/MC/RISCV/rv64e-valid.s
M llvm/test/MC/RISCV/rv64i-aliases-valid.s
M llvm/test/MC/RISCV/rv64i-valid.s
M llvm/test/MC/RISCV/rv64xtheadfmemidx-valid.s
M llvm/test/MC/RISCV/rv64zba-aliases-valid.s
M llvm/test/MC/RISCV/rv64zbb-aliases-valid.s
M llvm/test/MC/RISCV/rv64zbb-valid.s
M llvm/test/MC/RISCV/rv64zbkb-valid.s
M llvm/test/MC/RISCV/rv64zbs-aliases-valid.s
M llvm/test/MC/RISCV/rv64zknd-only-valid.s
M llvm/test/MC/RISCV/rv64zkne-only-valid.s
M llvm/test/MC/RISCV/rvc-aliases-valid.s
M llvm/test/MC/RISCV/rvc-hints-valid.s
M llvm/test/MC/RISCV/rvd-aliases-valid.s
M llvm/test/MC/RISCV/rvdc-aliases-valid.s
M llvm/test/MC/RISCV/rvf-aliases-valid.s
M llvm/test/MC/RISCV/rvi-aliases-valid.s
M llvm/test/MC/RISCV/rvi-alternate-abi-names.s
M llvm/test/MC/RISCV/rvv/add.s
M llvm/test/MC/RISCV/rvv/and.s
M llvm/test/MC/RISCV/rvv/clip.s
M llvm/test/MC/RISCV/rvv/compare.s
M llvm/test/MC/RISCV/rvv/mv.s
M llvm/test/MC/RISCV/rvv/or.s
M llvm/test/MC/RISCV/rvv/others.s
M llvm/test/MC/RISCV/rvv/rv32-immediate.s
M llvm/test/MC/RISCV/rvv/shift.s
M llvm/test/MC/RISCV/rvv/snippet.s
M llvm/test/MC/RISCV/rvv/sub.s
M llvm/test/MC/RISCV/rvv/vsetvl-invalid.s
M llvm/test/MC/RISCV/rvv/vsetvl.s
M llvm/test/MC/RISCV/rvv/xor.s
M llvm/test/MC/RISCV/rvv/xsfvcp.s
M llvm/test/MC/RISCV/rvv/zvbb.s
M llvm/test/MC/RISCV/rvv/zvfbfwma.s
M llvm/test/MC/RISCV/rvv/zvkb.s
M llvm/test/MC/RISCV/rvv/zvkned.s
M llvm/test/MC/RISCV/rvv/zvksed.s
M llvm/test/MC/RISCV/rvv/zvksh.s
M llvm/test/MC/RISCV/rvzfh-aliases-valid.s
M llvm/test/MC/RISCV/zicfilp-valid.s
M llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s
M llvm/test/tools/llvm-objdump/ELF/RISCV/multi-instr-target.s
M llvm/test/tools/llvm-objdump/ELF/RISCV/tag-riscv-arch.s
Log Message:
-----------
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
Enable the llvm-objdump to disassemble the immediate of RISCV
instruction in hexadecimal format with --print-imm-hex flag.
More information about the All-commits
mailing list