[all-commits] [llvm/llvm-project] f4b5be: Reapply "RegisterCoalescer: Add implicit-def of su...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f4b5be1ecdc85ca4257b739afb8d57e23c7a8030
      https://github.com/llvm/llvm-project/commit/f4b5be1ecdc85ca4257b739afb8d57e23c7a8030
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-12-15 (Fri, 15 Dec 2023)

  Changed paths:
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
    A llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
    M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
    A llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
    A llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir

  Log Message:
  -----------
  Reapply "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG"

This reverts commit 69c4930aad9659ec6ab846c8e7124d6afe044b1e.

See if this sticks after a few more coalescer assertions are fixed.