[all-commits] [llvm/llvm-project] 632f1c: [RISCV] When VLEN is exactly known, prefer VLMAX e...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 632f1c5d184b8adb7bf1bded357ccffeb5c2c5e2
      https://github.com/llvm/llvm-project/commit/632f1c5d184b8adb7bf1bded357ccffeb5c2c5e2
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-12-13 (Wed, 13 Dec 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll

  Log Message:
  -----------
  [RISCV] When VLEN is exactly known, prefer VLMAX encoding for vsetvli (#75412)

If we know the exact VLEN, then we can tell if the AVL for particular
operation is equivalent to the vsetvli xN, zero, <vtype> encoding. Using
this encoding is better than having to materialize an immediate in a
register, but worse than being able to use the vsetivli zero, imm,
<type> encoding.