[all-commits] [llvm/llvm-project] 6095e2: [RISCV] Bump zicfilp to 0.4 (#75134)
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Wed Dec 13 11:24:44 PST 2023
Branch: refs/heads/users/vitalybuka/spr/main.lsan-install-pthread_atfork
Home: https://github.com/llvm/llvm-project
Commit: 6095e211303d1c9b8bc2eb184c919d0b56bfe7e0
https://github.com/llvm/llvm-project/commit/6095e211303d1c9b8bc2eb184c919d0b56bfe7e0
Author: Yeting Kuo <46629943+yetingk at users.noreply.github.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Bump zicfilp to 0.4 (#75134)
Bump to https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0. Actually
there is no functional change here.
Commit: 912506b75d8a508353a701c230e73ca45a253161
https://github.com/llvm/llvm-project/commit/912506b75d8a508353a701c230e73ca45a253161
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2023-12-12 (Tue, 12 Dec 2023)
Changed paths:
M compiler-rt/test/sanitizer_common/TestCases/Posix/fork_threaded.c
Log Message:
-----------
[test][hwasan] Add `__hwasan_enable_allocator_tagging`
It's required for hwasan `aliasing` mode.
Commit: b003fed283d2d8dc0715964fcd84bd1298c75578
https://github.com/llvm/llvm-project/commit/b003fed283d2d8dc0715964fcd84bd1298c75578
Author: David Green <david.green at arm.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll
Log Message:
-----------
[CostModel] Add some ssa.copy costmodel tests. NFC
Commit: a01307a6ee788fc6ac2e09e58f0f52e5666def86
https://github.com/llvm/llvm-project/commit/a01307a6ee788fc6ac2e09e58f0f52e5666def86
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M clang/lib/Sema/SemaInit.cpp
M clang/test/Sema/missing-field-initializers.c
M clang/test/SemaCXX/cxx2a-initializer-aggregates.cpp
Log Message:
-----------
[clang] Fix false positive -Wmissing-field-initializer for anonymous unions (#70829)
Normally warning is not reported when a field has default initializer.
Do so for anonymous unions with default initializers as well. No release
note since it is a regression in clang 18.
Fixes https://github.com/llvm/llvm-project/issues/70384
Commit: a110e991c6795184c0960f75269b0b75cca51862
https://github.com/llvm/llvm-project/commit/a110e991c6795184c0960f75269b0b75cca51862
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
M llvm/test/TableGen/ContextlessPredicates.td
M llvm/test/TableGen/DefaultOpsGlobalISel.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-eraseroot.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-permutations.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
M llvm/test/TableGen/GlobalISelEmitter-PR39045.td
M llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td
M llvm/test/TableGen/GlobalISelEmitter-atomic_store.td
M llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td
M llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td
M llvm/test/TableGen/GlobalISelEmitter-input-discard.td
M llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td
M llvm/test/TableGen/GlobalISelEmitter-multiple-output.td
M llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
M llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td
M llvm/test/TableGen/GlobalISelEmitter-output-discard.td
M llvm/test/TableGen/GlobalISelEmitter-setcc.td
M llvm/test/TableGen/GlobalISelEmitter-zero-reg.td
M llvm/test/TableGen/GlobalISelEmitter.td
M llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td
M llvm/test/TableGen/GlobalISelEmitterFlags.td
M llvm/test/TableGen/GlobalISelEmitterHwModes.td
M llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td
M llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td
M llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td
M llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td
M llvm/test/TableGen/GlobalISelEmitterRegSequence.td
M llvm/test/TableGen/GlobalISelEmitterSubreg.td
M llvm/test/TableGen/GlobalISelEmitterVariadic.td
M llvm/test/TableGen/HasNoUse.td
M llvm/test/TableGen/address-space-patfrags.td
M llvm/test/TableGen/gisel-physreg-input.td
M llvm/test/TableGen/immarg-predicated.td
M llvm/test/TableGen/immarg.td
M llvm/test/TableGen/predicate-patfags.td
M llvm/utils/TableGen/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/GlobalISelMatchTable.h
M llvm/utils/TableGen/GlobalISelMatchTableExecutorEmitter.cpp
Log Message:
-----------
[GlobalISel] Change MatchTable entries to 1 byte each (#74429)
See
https://discourse.llvm.org/t/rfc-make-globalisel-match-table-entries-1-byte-instead-of-8/75411
This helps reduce llc's binary size, at the cost of some added
complexity to the MatchTable machinery.
Commit: dbf67ea1d334d2114fe49701a8f4b8afd536e39f
https://github.com/llvm/llvm-project/commit/dbf67ea1d334d2114fe49701a8f4b8afd536e39f
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaCXXScopeSpec.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/test/CXX/temp/temp.decls/temp.alias/p3.cpp
M clang/test/SemaCXX/alias-template.cpp
Log Message:
-----------
[clang] Substitute alias templates from correct context (#75069)
Current context set to where alias was met, not where it is declared
caused incorrect access check in case alias referenced private members
of the parent class.
This is a recommit of 6b1aa31 with a slight modification in order to fix
reported regression.
Fixes https://github.com/llvm/llvm-project/issues/41693
Commit: 06aa8b189ab3a13580d0abdcd5bf30ef22b119bd
https://github.com/llvm/llvm-project/commit/06aa8b189ab3a13580d0abdcd5bf30ef22b119bd
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
M llvm/include/llvm/CodeGen/GCMetadata.h
M llvm/include/llvm/CodeGen/MachinePassRegistry.def
M llvm/lib/CodeGen/GCMetadata.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
Log Message:
-----------
[CodeGen] Add analyses to help for porting GC passes (#74972)
- `CollectorMetadataAnalysis` provides `GCStrategyMap`.
- `GCFunctionAnalysis` provides `GCFunctionInfo`.
`GCStrategyMap` owns `GCStrategy` pointers and this
pass is used by `AsmPrinter` to iterate all GC strategies.
Most passes that require `GCModuleInfo` actually require the
`GCFunctionInfo`,
so add `GCFunctionAnalysis` for convenience.
Commit: f2b3e7c711ba440e87194002e9487c41d9bcf7d2
https://github.com/llvm/llvm-project/commit/f2b3e7c711ba440e87194002e9487c41d9bcf7d2
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
A llvm/test/MC/Disassembler/X86/avx512dq_vl.txt
A llvm/test/MC/X86/avx512dq_vl-att.s
A llvm/test/MC/X86/avx512dq_vl-intel.s
R llvm/test/MC/X86/intel-syntax-x86-avx512dq_vl.s
Log Message:
-----------
[X86][test] Add missing encoding/decoding tests for avx512dq_vl
Found in #75288
Commit: aee93cfe7ffe917c32e258c0d9767711fccc9d99
https://github.com/llvm/llvm-project/commit/aee93cfe7ffe917c32e258c0d9767711fccc9d99
Author: Fangrui Song <i at maskray.me>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Port 27259f17e9d273147c648331e92000a48677f489
Commit: 538a83e4b9ddaa6cc9e8680fa97b2e33cd03192d
https://github.com/llvm/llvm-project/commit/538a83e4b9ddaa6cc9e8680fa97b2e33cd03192d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
A llvm/test/CodeGen/X86/coalescer-partial-redundancy-clear-dead-flag-undef-copy.mir
Log Message:
-----------
RegisterCoalescer: Add undef flags in removePartialRedundancy (#75152)
If the copy being hoisted was undef, we have the same problems that
eliminateUndefCopy needs to solve. We would effectively be introducing a
new live out implicit_def. We need to add an undef flag to avoid
artificially introducing a live through undef value. Previously, the
verifier would fail due to the dead def inside the loop providing the
live in value for the %1 use.
Commit: a160536f8d142a7981576a98ec66802e0b4bb627
https://github.com/llvm/llvm-project/commit/a160536f8d142a7981576a98ec66802e0b4bb627
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
M llvm/test/TableGen/DefaultOpsGlobalISel.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-permutations.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
M llvm/test/TableGen/GlobalISelEmitter-input-discard.td
M llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
M llvm/test/TableGen/GlobalISelEmitter.td
M llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td
M llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td
M llvm/test/TableGen/GlobalISelEmitterRegSequence.td
M llvm/test/TableGen/GlobalISelEmitterSubreg.td
M llvm/utils/TableGen/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/GlobalISelMatchTable.h
Log Message:
-----------
[TableGen][GlobalISel] Add specialized opcodes (#74823)
Most users of AddImm and CheckConstantInt only use 1 byte immediates, so
I added an opcode variants for those. That way all those instructions
save 7 bytes.
Also added an opcode for AddTempRegister for the cases where there are
no register flags.
Space savings:
- AMDGPUGenGlobalISel: 470180 bytes to 422564 (-10%)
- AArch64GenGlobalISel.inc: 383893 bytes to 374046
Commit: 80bb994d2b17b7e116e76492b9d6ede07c72d82c
https://github.com/llvm/llvm-project/commit/80bb994d2b17b7e116e76492b9d6ede07c72d82c
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
A llvm/include/llvm/CodeGen/IndirectBrExpand.h
M llvm/include/llvm/CodeGen/MachinePassRegistry.def
M llvm/include/llvm/InitializePasses.h
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/IndirectBrExpandPass.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/test/Transforms/IndirectBrExpand/basic.ll
M llvm/tools/opt/opt.cpp
Log Message:
-----------
[CodeGen] Port `IndirectBrExpand` to new pass manager (#75287)
Commit: 2c0abdf2df9fc92a513433f009718b1bfd216020
https://github.com/llvm/llvm-project/commit/2c0abdf2df9fc92a513433f009718b1bfd216020
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M libc/src/stdlib/CMakeLists.txt
Log Message:
-----------
[libc] [riscv] support build with `scudo` on `riscv64` (#74951)
This patch fixes cmake configuration when building with
LLVM_LIBC_INCLUDE_SCUDO. In libc, LIBC_TARGET_ARCHITECTURE is renamed
from `riscv64` to `riscv`. However, `compiler-rt`, hence `scudo`,
distinguishes `riscv32` and `riscv64` in the support list. As a result,
we need to translate the architecture name accordingly.
Commit: 300a55003c7ef7b3a87844a88781e4fdcba860ff
https://github.com/llvm/llvm-project/commit/300a55003c7ef7b3a87844a88781e4fdcba860ff
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
A llvm/test/CodeGen/X86/coalescer-dead-flag-verifier-error.ll
A llvm/test/CodeGen/X86/coalescer-remat-with-undef-implicit-def-operand.mir
Log Message:
-----------
RegisterCoalescer: Fix implicit operand handling during rematerialize (#75271)
If the rematerialize was placing a subregister into a super register,
and implicit operands referenced the original register, we need to add
undef flags to the now-subregister indexed implicit operands.
Depends #75152
Commit: 60eca674b16a64957c43aba6a05fb32d2413ed72
https://github.com/llvm/llvm-project/commit/60eca674b16a64957c43aba6a05fb32d2413ed72
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
A llvm/include/llvm/CodeGen/ExpandMemCmp.h
M llvm/include/llvm/CodeGen/MachinePassRegistry.def
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/LinkAllPasses.h
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/ExpandMemCmp.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll
M llvm/test/Transforms/ExpandMemCmp/AArch64/memcmp.ll
M llvm/test/Transforms/ExpandMemCmp/X86/bcmp.ll
M llvm/test/Transforms/ExpandMemCmp/X86/memcmp-x32.ll
M llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll
M llvm/tools/opt/opt.cpp
Log Message:
-----------
[CodeGen] Port `ExpandMemCmp` to new pass manager (#74050)
Commit: f64a0576ad4fbdf6a514ae89f90814c8f4c6e254
https://github.com/llvm/llvm-project/commit/f64a0576ad4fbdf6a514ae89f90814c8f4c6e254
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/Hypot.h
M libc/src/__support/FPUtil/generic/FMod.h
M libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
M libc/src/__support/str_to_float.h
M libc/src/math/generic/acoshf.cpp
M libc/src/math/generic/asinhf.cpp
M libc/src/math/generic/atanhf.cpp
M libc/src/math/generic/erff.cpp
M libc/src/math/generic/explogxf.h
M libc/src/math/generic/inv_trigf_utils.h
M libc/src/math/generic/log.cpp
M libc/src/math/generic/log10.cpp
M libc/src/math/generic/log1p.cpp
M libc/src/math/generic/log2.cpp
M libc/src/math/generic/sinhf.cpp
M libc/src/math/generic/tanhf.cpp
Log Message:
-----------
[libc][NFC] Implement `FPBits` in terms of `FloatProperties` to reduce clutter (#75196)
Also make type naming consistent:
- `UIntType` instead of `intU_t`
- `FPBits` instead of `FPBits_t`, `FPB`
Commit: 84ab06ba2f37252ab40f84c39f17addce63eaa88
https://github.com/llvm/llvm-project/commit/84ab06ba2f37252ab40f84c39f17addce63eaa88
Author: Abhinav271828 <71174780+Abhinav271828 at users.noreply.github.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M mlir/include/mlir/Analysis/Presburger/Matrix.h
M mlir/include/mlir/Analysis/Presburger/Utils.h
M mlir/lib/Analysis/Presburger/Matrix.cpp
M mlir/lib/Analysis/Presburger/Utils.cpp
M mlir/unittests/Analysis/Presburger/MatrixTest.cpp
Log Message:
-----------
[MLIR][Presburger] Add Gram-Schmidt (#70843)
Implement Gram-Schmidt orthogonalisation for the FracMatrix class.
This requires dotProduct, which has been added as a util.
Commit: b493793850e626490364816ec04fe12cd04fa362
https://github.com/llvm/llvm-project/commit/b493793850e626490364816ec04fe12cd04fa362
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
A llvm/test/MC/Disassembler/X86/avx512_bf16.txt
R llvm/test/MC/Disassembler/X86/avx512bf16-att.txt
R llvm/test/MC/Disassembler/X86/avx512bf16-intel.txt
A llvm/test/MC/X86/avx512_bf16-att.s
R llvm/test/MC/X86/avx512_bf16-encoding.s
A llvm/test/MC/X86/avx512_bf16-intel.s
R llvm/test/MC/X86/intel-syntax-avx512_bf16.s
Log Message:
-----------
[X86][test] Merge the decoding tests for avx512_bf16 and unify the names
Commit: 5b32740631252dd38f41b818a12b28880b02c3b4
https://github.com/llvm/llvm-project/commit/5b32740631252dd38f41b818a12b28880b02c3b4
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
A llvm/test/MC/Disassembler/X86/avx512bitalg.txt
A llvm/test/MC/X86/avx512bitalg-att.s
R llvm/test/MC/X86/avx512bitalg-encoding.s
A llvm/test/MC/X86/avx512bitalg-intel.s
Log Message:
-----------
[X86][test] Add missing encoding/decoding tests for avx512bitalg
Commit: a9af317fbecae00508b3f8c752af3dbcc06e2fcb
https://github.com/llvm/llvm-project/commit/a9af317fbecae00508b3f8c752af3dbcc06e2fcb
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/Hypot.h
M libc/src/__support/FPUtil/generic/FMod.h
M libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
M libc/src/__support/str_to_float.h
M libc/src/math/generic/acoshf.cpp
M libc/src/math/generic/asinhf.cpp
M libc/src/math/generic/atanhf.cpp
M libc/src/math/generic/erff.cpp
M libc/src/math/generic/explogxf.h
M libc/src/math/generic/inv_trigf_utils.h
M libc/src/math/generic/log.cpp
M libc/src/math/generic/log10.cpp
M libc/src/math/generic/log1p.cpp
M libc/src/math/generic/log2.cpp
M libc/src/math/generic/sinhf.cpp
M libc/src/math/generic/tanhf.cpp
Log Message:
-----------
Revert "[libc][NFC] Implement `FPBits` in terms of `FloatProperties` to reduce clutter" (#75304)
Reverts llvm/llvm-project#75196
GCC complains about change of meaning for `FPBits`
```
/home/llvm-libc-buildbot/buildbot-worker/libc-x86_64-debian-fullbuild/libc-x86_64-debian-gcc-fullbuild-dbg/llvm-project/libc/src/__support/FPUtil/generic/FMod.h:188:9: error: declaration of ‘using FPBits = struct __llvm_libc_18_0_0_git::fputil::FPBits<T>’ changes meaning of ‘FPBits’ [-fpermissive]
188 | using FPBits = FPBits<T>;
| ^~~~~~
```
I'll reland with a different name.
Commit: 41aa0d4690a25366a5acbd4f3cbc94ca89176dfe
https://github.com/llvm/llvm-project/commit/41aa0d4690a25366a5acbd4f3cbc94ca89176dfe
Author: Nikita Popov <npopov at redhat.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/include/llvm/MC/MCFragment.h
Log Message:
-----------
[MC] Reduce size of MCLEBFragment (NFC) (#75050)
This recovers more of the max-rss regression introduced by
https://reviews.llvm.org/D157657.
This is an about 1.2% max-rss improvement for the LTO link stage with
debuginfo on CTMark.
Commit: ed2d497291f0de330e27109ce21375b41597b4a4
https://github.com/llvm/llvm-project/commit/ed2d497291f0de330e27109ce21375b41597b4a4
Author: CarolineConcatto <caroline.concatto at arm.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Sema/SemaType.cpp
A clang/test/CodeGen/arm-vector_type-params-returns.c
M clang/test/Sema/aarch64-sve-intrinsics/acle_sve_target.cpp
M clang/test/Sema/arm-vector-types-support.c
M clang/test/SemaCUDA/neon-attrs.cu
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
Log Message:
-----------
[Clang][AArch64] Add fix vector types to header into SVE (#73258)
This patch is needed for the reduction instructions in sve2.1
It add a new header to sve with all the fixed vector types.
The new types are only added if neon is not declared.
Commit: dcbf1e4e49f3253c8633edeb4e91694631d61b81
https://github.com/llvm/llvm-project/commit/dcbf1e4e49f3253c8633edeb4e91694631d61b81
Author: Greg Clayton <gclayton at fb.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M lldb/test/API/lang/cpp/union-static-data-members/TestCppUnionStaticMembers.py
M lldb/unittests/SymbolFile/PDB/SymbolFilePDBTests.cpp
Log Message:
-----------
[lldb] Fix buildbots after PR 74786 (#75272)
Fix unexpected pass after
https://github.com/llvm/llvm-project/pull/74786.
Commit: 96ab8ef999188e26c5d79521872826a199ee33ac
https://github.com/llvm/llvm-project/commit/96ab8ef999188e26c5d79521872826a199ee33ac
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
R llvm/test/MC/Disassembler/X86/avx512bf16vl-att.txt
R llvm/test/MC/Disassembler/X86/avx512bf16vl-intel.txt
R llvm/test/MC/Disassembler/X86/x86-64-avx512bf16vl-att.txt
R llvm/test/MC/Disassembler/X86/x86-64-avx512bf16vl-intel.txt
A llvm/test/MC/Disassembler/avx512_bf16_vl-32.txt
A llvm/test/MC/Disassembler/avx512_bf16_vl-64.txt
A llvm/test/MC/X86/avx512_bf16_vl-32-att.s
A llvm/test/MC/X86/avx512_bf16_vl-32-intel.s
A llvm/test/MC/X86/avx512_bf16_vl-64-att.s
A llvm/test/MC/X86/avx512_bf16_vl-64-intel.s
R llvm/test/MC/X86/avx512_bf16_vl-encoding.s
R llvm/test/MC/X86/intel-syntax-avx512_bf16_vl.s
R llvm/test/MC/X86/intel-syntax-x86-64-avx512_bf16_vl.s
R llvm/test/MC/X86/x86-64-avx512_bf16_vl-encoding.s
Log Message:
-----------
[X86][test] Merge the decoding tests for avx512_bf16_vl and unify the names
Commit: d7ee99a4fc1108d6d5ae1b28cb71a57530723fc7
https://github.com/llvm/llvm-project/commit/d7ee99a4fc1108d6d5ae1b28cb71a57530723fc7
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/CodeGen/MachineSink.cpp
A llvm/test/CodeGen/AArch64/sink-and-fold-clear-kill-flags.mir
Log Message:
-----------
[MachineSink] Clear kill flags of sunk addressing mode registers (#75072)
When doing sink-and-fold, the MachineSink clears the "killed" flags of
the operands of the sunk (and deleted) instruction. However, this is not
always sufficient. In some cases we can create the new load/store
instruction with operands other than the ones present in the deleted
instruction. One such example is folding a zero word extend into a
memory load on AArch64. The zero-extend is represented by a pair of
instructions - `MOV` (i.e. `ORRwrs`) followed by a `SUBREG_TO_REG`. The
`SUBREG_TO_REG` is deleted (it is the sunk instruction), but the new
load instruction mentions operands "killed" in the `MOV`, which is no
longer correct.
To fix this, clear the "killed" flags of the registers participating in
the addressing mode.
Commit: 1c494198c3f2abc3b10b02e704a0129de74e47d2
https://github.com/llvm/llvm-project/commit/1c494198c3f2abc3b10b02e704a0129de74e47d2
Author: Z572 <zhengjunjie at iscas.ac.cn>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/test/Transforms/InstCombine/div.ll
Log Message:
-----------
[InstCombine] simplify `(X * C0) / (X * C1)` into `C0 / C1`. (#73204)
fix #72114
proof: https://alive2.llvm.org/ce/z/xqprFm
Commit: ed5813c4aafef81aa8e22b3e252b687c611fcbd0
https://github.com/llvm/llvm-project/commit/ed5813c4aafef81aa8e22b3e252b687c611fcbd0
Author: Johannes de Fine Licht <johannes.definelicht at nextsilicon.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMInlining.cpp
Log Message:
-----------
[MLIR][LLVM] Remove disallowlist from LLVM inliner (#75303)
The disallowlist was used as a migration strategy while support was
extended to more side effecting operations. We now (to the best of our
knowledge) support all side effecting operations, so never fail
`isLegalToInline` on any LLVM operation.
There is no test included, because that's exactly the reason for this
change: there are no more unsupported operations in inlining; the
existing tests for unsupported inlines have already been burninated.
Commit: 65dea5cc7208c42a803acbd125933b61cefc6f6e
https://github.com/llvm/llvm-project/commit/65dea5cc7208c42a803acbd125933b61cefc6f6e
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
A llvm/test/MC/Disassembler/X86/avx512_bf16-32.txt
A llvm/test/MC/Disassembler/X86/avx512_bf16-64.txt
R llvm/test/MC/Disassembler/X86/avx512_bf16.txt
R llvm/test/MC/Disassembler/X86/x86-64-avx512bf16-att.txt
R llvm/test/MC/Disassembler/X86/x86-64-avx512bf16-intel.txt
A llvm/test/MC/X86/avx512_bf16-32-att.s
A llvm/test/MC/X86/avx512_bf16-32-intel.s
A llvm/test/MC/X86/avx512_bf16-64-att.s
A llvm/test/MC/X86/avx512_bf16-64-intel.s
R llvm/test/MC/X86/avx512_bf16-att.s
R llvm/test/MC/X86/avx512_bf16-intel.s
R llvm/test/MC/X86/intel-syntax-x86-64-avx512_bf16.s
R llvm/test/MC/X86/x86-64-avx512_bf16-encoding.s
Log Message:
-----------
[X86][test] Merge the decoding tests for avx512_bf16 and unify the names
Commit: eab62971cda97bd0f9d66944ef295946c291563f
https://github.com/llvm/llvm-project/commit/eab62971cda97bd0f9d66944ef295946c291563f
Author: Christian Ulmann <christianulmann at gmail.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/Import/global-variables.ll
M mlir/test/Target/LLVMIR/llvmir-debug.mlir
Log Message:
-----------
[MLIR][LLVM] Support nameless and scopeless global constants (#75307)
This commit ensures that we model DI information for global constants
correctly. These constructs can lack scopes, names, and linkage names,
so these parameters were made optional for the DIGlobalVariable
attribute.
Commit: 41f905ddf007b08afa41e3e22326ecea446f2cfe
https://github.com/llvm/llvm-project/commit/41f905ddf007b08afa41e3e22326ecea446f2cfe
Author: Nikita Popov <npopov at redhat.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
A llvm/test/Transforms/CorrelatedValuePropagation/cond-using-block-value.ll
Log Message:
-----------
[CVP] Add tests for using block values in conditions (NFC)
Commit: 1e5338669026e1be1e0b0b8fc886cbd949616be8
https://github.com/llvm/llvm-project/commit/1e5338669026e1be1e0b0b8fc886cbd949616be8
Author: David Spickett <david.spickett at linaro.org>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/docs/TableGen/index.rst
M llvm/utils/TableGen/README.md
Log Message:
-----------
[llvm][TableGen][Docs] Add tools/resources links
This adds a link from the main docs page back to the README where
I have previously added a list of useful resources.
To that list, I've added a link to my recent llvm blog post.
Commit: d36f72b4187c3d934fd0558d174ad0c5ecafe140
https://github.com/llvm/llvm-project/commit/d36f72b4187c3d934fd0558d174ad0c5ecafe140
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
Log Message:
-----------
[clang][Sema][NFC] Add a boolean parameter comment
Commit: 62653573cbed2bf4b13de3dd73c1b9f8da60677f
https://github.com/llvm/llvm-project/commit/62653573cbed2bf4b13de3dd73c1b9f8da60677f
Author: Piotr Sobczak <piotr.sobczak at amd.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/Target/AMDGPU/SIDefines.h
Log Message:
-----------
[AMDGPU] Extend clang-format directive in SIDefines.h
Commit: 92433285d7b30023249e68ff1706f1cd4e73ad18
https://github.com/llvm/llvm-project/commit/92433285d7b30023249e68ff1706f1cd4e73ad18
Author: Georgios Pinitas <georgios.pinitas at arm.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M mlir/include/mlir/Dialect/ArmSME/Transforms/CMakeLists.txt
Log Message:
-----------
[mlir][ArmSME] Add missing dependencies in ArmSME transforms (#75269)
Inject missing dependency between generated files that could cause build
issues.
Signed-off-by: Georgios Pinitas <georgios.pinitas at arm.com>
Commit: 9505cf457fe1b3927ff769f55f7eb2bfcce0a552
https://github.com/llvm/llvm-project/commit/9505cf457fe1b3927ff769f55f7eb2bfcce0a552
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-read-2d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-write-2d.mlir
Log Message:
-----------
[mlir][ArmSME][test] Use `only-if-required-by-ops` rather than `enable_arm_streaming_ignore` (NFC) (#75209)
This moves the fix out of the IR and into the pass description, which
seems nicer. It also works as an integration test for the
`only-if-required-by-ops` flag :)
Commit: 869133771af2762a7835c5691063f81675cd0ece
https://github.com/llvm/llvm-project/commit/869133771af2762a7835c5691063f81675cd0ece
Author: Stephan T. Lavavej <stl at nuwen.net>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M libcxx/include/__ranges/lazy_split_view.h
M libcxx/include/__ranges/split_view.h
M libcxx/test/std/ranges/range.adaptors/range.lazy.split/adaptor.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.split/adaptor.pass.cpp
Log Message:
-----------
[libc++] `views::split` and `views::lazy_split` shouldn't be range adaptor closures (#75266)
Fixes #75002. Found while running libc++'s tests with MSVC's STL.
This is a superset of #74961 that also fixes the product code
and adds a regression test. Thanks again, @cpplearner!
To summarize: `views::split` and `views::lazy_split` aren't unary,
aren't range adaptor **closure** objects, and can't be piped. However,
\[range.adaptor.object\]/8 says that `views::split(pattern)` and
`views::lazy_split(pattern)` produce unary, pipeable, range adaptor
closure objects.
This PR adjusts the test coverage accordingly, allowing it to portably
pass for libc++ and MSVC's STL.
Commit: f78024c8551855d130645dc89a871c4e2b0af020
https://github.com/llvm/llvm-project/commit/f78024c8551855d130645dc89a871c4e2b0af020
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M lld/COFF/Driver.cpp
M lld/test/COFF/Inputs/loadconfig-arm64ec.s
M lld/test/COFF/Inputs/loadconfig-cfg-x64.s
A lld/test/COFF/merge-00cfg.s
Log Message:
-----------
[lld][COFF] Merge .00cfg section into .rdata. (#75207)
.00cfg section is used by crt for load config and is merged by MS
link.exe into .rdata.
Commit: effd47ed45e3badd756103346a7c3b9e1e939e5e
https://github.com/llvm/llvm-project/commit/effd47ed45e3badd756103346a7c3b9e1e939e5e
Author: Jay Foad <jay.foad at amd.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M clang/test/CodeGen/arm-vector_type-params-returns.c
Log Message:
-----------
[Clang][AArch64] Add REQUIRES to new test
Commit: d293a354d076c772ccd2972a71cb4a7d6f9aa410
https://github.com/llvm/llvm-project/commit/d293a354d076c772ccd2972a71cb4a7d6f9aa410
Author: john-brawn-arm <john.brawn at arm.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/test/tools/llvm-readobj/ELF/AArch64/aarch64-note-gnu-property.s
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[AArch64][ELF][llvm-readobj] Support the GCS .note.gnu.property bit (#75065)
This bit was added to the AArch64 ABI by
https://github.com/ARM-software/abi-aa/pull/231.
Commit: 358e7656807f7a459baa0ad6002dd246fbad88e3
https://github.com/llvm/llvm-project/commit/358e7656807f7a459baa0ad6002dd246fbad88e3
Author: Bruno De Fraine <brunodf at synopsys.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
A llvm/test/Transforms/LICM/variant-aainfo.ll
Log Message:
-----------
[LICM] Add test show missed promotion due to AAInfo merging (NFC)
Commit: bb18611e3630d956b74fe33209321cb8ba9272a8
https://github.com/llvm/llvm-project/commit/bb18611e3630d956b74fe33209321cb8ba9272a8
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
A llvm/test/MC/Disassembler/X86/avx512_bf16_vl-32.txt
A llvm/test/MC/Disassembler/X86/avx512_bf16_vl-64.txt
R llvm/test/MC/Disassembler/avx512_bf16_vl-32.txt
R llvm/test/MC/Disassembler/avx512_bf16_vl-64.txt
Log Message:
-----------
[X86][test] Move the x86 tests to correct folder
This is a fix for 96ab8ef999188e26c5d79521872826a199ee33ac
Commit: a8977005b64986139e92b5a43e44cfac2bf81677
https://github.com/llvm/llvm-project/commit/a8977005b64986139e92b5a43e44cfac2bf81677
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M clang/lib/AST/Interp/Interp.cpp
M clang/test/AST/Interp/functions.cpp
Log Message:
-----------
[clang][Interp] Don't diagnose undefined functions when checking... (#75051)
... for a potential constant expression. They are not defined now, but
might be defined later when the function is actually called.
Commit: c0307789796150699b550a314be236ea0b1be9ed
https://github.com/llvm/llvm-project/commit/c0307789796150699b550a314be236ea0b1be9ed
Author: Bruno De Fraine <brunodf at synopsys.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/include/llvm/Analysis/AliasSetTracker.h
M llvm/include/llvm/LinkAllPasses.h
M llvm/lib/Analysis/AliasSetTracker.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
Log Message:
-----------
[AST] Switch to MemoryLocation in add method (NFC)
Pass MemoryLocation as one argument, instead of passing all its
parts separately.
Commit: 887f2110280fd9a37003fd2bb811c6c1dcf4370d
https://github.com/llvm/llvm-project/commit/887f2110280fd9a37003fd2bb811c6c1dcf4370d
Author: David Spickett <david.spickett at linaro.org>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M lldb/unittests/SymbolFile/PDB/SymbolFilePDBTests.cpp
Log Message:
-----------
[lldb][PDB] Attempt to fix tests on Windows
Commit: 65d3548f7d8904320d330ac9fd2eb14a763a8c1f
https://github.com/llvm/llvm-project/commit/65d3548f7d8904320d330ac9fd2eb14a763a8c1f
Author: Nico Weber <thakis at chromium.org>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn] port 9ed20568e7de
Commit: 3c9236c0bf57a3a7689fc64c57c1325ea466b1c0
https://github.com/llvm/llvm-project/commit/3c9236c0bf57a3a7689fc64c57c1325ea466b1c0
Author: Bruno De Fraine <brunodf at synopsys.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp
Log Message:
-----------
[LoopVersioningLICM] add comment regarding dubious check (NFC)
Commit: bdbc2db5360e043c7e32cabeaa230cf91f5e51e2
https://github.com/llvm/llvm-project/commit/bdbc2db5360e043c7e32cabeaa230cf91f5e51e2
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/IR/BasicBlock.cpp
Log Message:
-----------
[RemoveDIs] Enable conversion from dbg.declare to DPValue (#74090)
Note that all the patches that implement support for declare-style
DPValues have tests that are "rotten green" test without this
patch (i.e., they pass at the moment without testing what we
want them to test). See the Pull Request for more detail on this.
Commit: 213c49807fcfbdac2543b1ce16c9ca3ccf81e6fc
https://github.com/llvm/llvm-project/commit/213c49807fcfbdac2543b1ce16c9ca3ccf81e6fc
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/generic/FMod.h
M libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
M libc/src/__support/str_to_float.h
M libc/src/math/generic/acoshf.cpp
M libc/src/math/generic/asinhf.cpp
M libc/src/math/generic/atanhf.cpp
M libc/src/math/generic/erff.cpp
M libc/src/math/generic/explogxf.h
M libc/src/math/generic/inv_trigf_utils.h
M libc/src/math/generic/log1p.cpp
M libc/src/math/generic/sinhf.cpp
M libc/src/math/generic/tanhf.cpp
Log Message:
-----------
[reland][libc][NFC] Implement `FPBits` in terms of `FloatProperties` to reduce clutter (#75196) (#75318)
Also make type naming consistent by using `UIntType` instead of
`intU_t`.
This patch is a reland of #75196 but does not include the "use `FPBits`
instead of `FPBits_t`, `FPB`" part. This needs more work.
Commit: 490c3aaca9f069904cc3c00a13cdcdcec7de0eb0
https://github.com/llvm/llvm-project/commit/490c3aaca9f069904cc3c00a13cdcdcec7de0eb0
Author: XinWang10 <108658776+XinWang10 at users.noreply.github.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/test/MC/Disassembler/X86/avx512dq_vl.txt
M llvm/test/MC/X86/avx512dq_vl-att.s
M llvm/test/MC/X86/avx512dq_vl-intel.s
Log Message:
-----------
[X86][MC] Pre-commit test for 74713 (#75288)
Commit: 7433120137277b08f4b412f7b549a24410009fb3
https://github.com/llvm/llvm-project/commit/7433120137277b08f4b412f7b549a24410009fb3
Author: David Green <david.green at arm.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll
Log Message:
-----------
[CostModel] Mark ssa_copy as free (#75294)
These are intrinsics are only used ephemerally and be should be given a
zero cost.
Commit: 762964e97fd66ab7728ecc92aa153a61266fa9df
https://github.com/llvm/llvm-project/commit/762964e97fd66ab7728ecc92aa153a61266fa9df
Author: Sungsoon Cho <1025787+godot73 at users.noreply.github.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M mlir/include/mlir/Dialect/Math/IR/MathOps.td
M mlir/lib/Conversion/MathToLibm/MathToLibm.cpp
M mlir/lib/Dialect/Math/IR/MathOps.cpp
M mlir/test/Conversion/MathToLibm/convert-to-libm.mlir
Log Message:
-----------
Add cosh op to the math dialect. (#75153)
Commit: 7c944dc946048671574800802353373b6586cb2c
https://github.com/llvm/llvm-project/commit/7c944dc946048671574800802353373b6586cb2c
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
A llvm/test/MC/Disassembler/X86/avx512vbmi.txt
A llvm/test/MC/X86/avx512vbmi-att.s
R llvm/test/MC/X86/avx512vbmi-encoding.s
A llvm/test/MC/X86/avx512vbmi-intel.s
Log Message:
-----------
[X86][test] Add missing encoding/decoding tests for avx512vbmi and unify the names
Commit: 35dacf2f51af251a74ac98ed29e7c454a619fcf1
https://github.com/llvm/llvm-project/commit/35dacf2f51af251a74ac98ed29e7c454a619fcf1
Author: David Spickett <david.spickett at linaro.org>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
R lldb/test/API/python_api/global_module_cache/Makefile
R lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py
R lldb/test/API/python_api/global_module_cache/one-print.c
R lldb/test/API/python_api/global_module_cache/two-print.c
Log Message:
-----------
Revert "Add a test for evicting unreachable modules from the global module cache (#74894)"
This reverts commit 2684281d208612a746b05c891f346bd7b95318d5.
Due to being flaky on Arm and AArch64 buildbots.
Commit: 6fe3cd54670cae52dae92a38a6d28f450fe8f321
https://github.com/llvm/llvm-project/commit/6fe3cd54670cae52dae92a38a6d28f450fe8f321
Author: Benjamin Chetioui <3920784+bchetioui at users.noreply.github.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M mlir/lib/Transforms/Utils/FoldUtils.cpp
Log Message:
-----------
[MLIR][NFC] Add fast path to fused loc flattening. (#75312)
This is a follow-up on [PR
75218](https://github.com/llvm/llvm-project/pull/75218) that avoids
reconstructing a fused loc in the `FlattenFusedLocationRecursively`
helper when there has been no change.
Commit: e34c35a21ccc215ce507a1e19b4ff2a1ce9906f3
https://github.com/llvm/llvm-project/commit/e34c35a21ccc215ce507a1e19b4ff2a1ce9906f3
Author: David Spickett <david.spickett at linaro.org>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M lldb/unittests/SymbolFile/PDB/SymbolFilePDBTests.cpp
Log Message:
-----------
[lldb][PDB] Fix more issues with PDB tests
Commit: ea0e9cbdc0592af1dc0284ed73df7a3fb42749ba
https://github.com/llvm/llvm-project/commit/ea0e9cbdc0592af1dc0284ed73df7a3fb42749ba
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
A llvm/test/MC/Disassembler/X86/avx512vp2intersect-32.txt
A llvm/test/MC/Disassembler/X86/avx512vp2intersect-64.txt
A llvm/test/MC/X86/avx512vp2intersect-32-att.s
A llvm/test/MC/X86/avx512vp2intersect-32-intel.s
A llvm/test/MC/X86/avx512vp2intersect-64-att.s
A llvm/test/MC/X86/avx512vp2intersect-64-intel.s
R llvm/test/MC/X86/x86-32-avx512vp2intersect-att.s
R llvm/test/MC/X86/x86-64-avx512vp2intersect-att.s
Log Message:
-----------
[X86][test] Add missing encoding/decoding tests for avx512vp2intersect and unify the names
Commit: a29457844bf0c4b2eb5c0f3877b6e8ef30cdef52
https://github.com/llvm/llvm-project/commit/a29457844bf0c4b2eb5c0f3877b6e8ef30cdef52
Author: mohammed-nurulhoque <96180492+mohammed-nurulhoque at users.noreply.github.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
M llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
A llvm/test/CodeGen/RISCV/dead-stack-slot.ll
M llvm/test/DebugInfo/COFF/lexicalblock.ll
Log Message:
-----------
[StackColoring] Delete dead stack slots (#72633)
Deletes slots that have lifetime markers and the lifetime ranges are
empty.
Commit: 3fef50f3682ecdd5db748903a029cadb031cf1ee
https://github.com/llvm/llvm-project/commit/3fef50f3682ecdd5db748903a029cadb031cf1ee
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
R llvm/test/MC/X86/x86-32-avx512_vp2intersect-intel.s
R llvm/test/MC/X86/x86-64-avx512_vp2intersect-intel.s
Log Message:
-----------
[X86][test] Remove duplicated tests for avx512_vp2intersect
They're duplicated with
llvm/test/MC/X86/avx512vp2intersect-32-intel.s
llvm/test/MC/X86/avx512vp2intersect-64-intel.s
Commit: e418988175c2dee9d7c7976cf822b41aaf321c26
https://github.com/llvm/llvm-project/commit/e418988175c2dee9d7c7976cf822b41aaf321c26
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
A llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-32.txt
A llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-64.txt
R llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-att.txt
R llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-intel.txt
R llvm/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-att.txt
R llvm/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-intel.txt
A llvm/test/MC/X86/avx512vp2intersectvl-32-att.s
A llvm/test/MC/X86/avx512vp2intersectvl-32-intel.s
A llvm/test/MC/X86/avx512vp2intersectvl-64-att.s
A llvm/test/MC/X86/avx512vp2intersectvl-64-intel.s
R llvm/test/MC/X86/avx512vp2intersectvl-att.s
R llvm/test/MC/X86/avx512vp2intersectvl-intel.s
R llvm/test/MC/X86/x86-64-avx512vp2intersectvl-att.s
R llvm/test/MC/X86/x86-64-avx512vp2intersectvl-intel.s
Log Message:
-----------
[X86][test] Merge the decoding tests for avx512vp2intersectvl and unify the names
Commit: fd8fa31c55a3413f643443ecf3301441428ce513
https://github.com/llvm/llvm-project/commit/fd8fa31c55a3413f643443ecf3301441428ce513
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Coroutines/CoroInternal.h
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/test/Transforms/Coroutines/coro-debug-O2.ll
M llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll
M llvm/test/Transforms/Coroutines/coro-debug-dbg.values-not_used_in_frame.ll
M llvm/test/Transforms/Coroutines/coro-debug-dbg.values.ll
M llvm/test/Transforms/Coroutines/coro-debug-frame-variable.ll
M llvm/test/Transforms/Coroutines/coro-debug-spill-dbg.declare.ll
M llvm/test/Transforms/Coroutines/coro-debug.ll
M llvm/test/Transforms/Coroutines/coro-split-dbg.ll
M llvm/test/Transforms/Coroutines/swift-async-dbg.ll
Log Message:
-----------
[RemoveDIs] Update Coroutine passes to handle DPValues (#74480)
As part of the RemoveDIs project, transitioning to non-instruction debug
info, all debug intrinsic handling code needs to be duplicated to handle
DPValues.
--try-experimental-debuginfo-iterators enables the new debug mode in
tests if the CMake option has been enabled.
`getInsertPtAfterFramePtr` now returns an iterator so we don't lose
debug-info-communicating bits.
---
Depends on #73500, #74090, #74091.
Commit: ab380c287a42c0701cd86ae2932c0cb125b9a294
https://github.com/llvm/llvm-project/commit/ab380c287a42c0701cd86ae2932c0cb125b9a294
Author: Abhina Sree <69635948+abhina-sree at users.noreply.github.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M clang/tools/c-arcmt-test/c-arcmt-test.c
M clang/tools/c-index-test/c-index-test.c
M llvm/include/llvm/Support/AutoConvert.h
M llvm/lib/Support/AutoConvert.cpp
M llvm/lib/Support/InitLLVM.cpp
M llvm/lib/Support/Unix/Program.inc
M llvm/lib/Support/raw_ostream.cpp
M llvm/utils/count/CMakeLists.txt
M llvm/utils/count/count.c
Log Message:
-----------
[SystemZ][z/OS] Complete EBCDIC I/O support (#75212)
This patch completes the support for EBCDIC I/O support on z/OS using the autoconversion functions.
Commit: f59fed261e30ddeecb6c6bfb53e47ecd4b124e7a
https://github.com/llvm/llvm-project/commit/f59fed261e30ddeecb6c6bfb53e47ecd4b124e7a
Author: David Spickett <david.spickett at linaro.org>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M lldb/unittests/SymbolFile/PDB/SymbolFilePDBTests.cpp
Log Message:
-----------
[lldb][PDB] TypeQuery parameter should be ConstString
Commit: 4fc604899f551826fc850a00cce5def0ccafb653
https://github.com/llvm/llvm-project/commit/4fc604899f551826fc850a00cce5def0ccafb653
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
M llvm/test/Transforms/Util/trivial-auto-var-init-call.ll
M llvm/test/Transforms/Util/trivial-auto-var-init-store.ll
Log Message:
-----------
[RemoveDIs] Support DPValue dbg.declares in MemoryOpRemark (#74108)
Depends on #74099, #73500.
Commit: fac093dd08cc3c71e4ba0f08f696e81b670f3cc8
https://github.com/llvm/llvm-project/commit/fac093dd08cc3c71e4ba0f08f696e81b670f3cc8
Author: Piotr Sobczak <piotr.sobczak at amd.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/Support/AMDHSAKernelDescriptor.h
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.cpp
M llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.h
M llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
A llvm/test/MC/AMDGPU/hsa-gfx12-v4.s
Log Message:
-----------
[AMDGPU] Update IEEE and DX10_CLAMP for GFX12 (#75030)
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Commit: c2d3188d5dcb8158d9b8fa2a85f984fc621c7044
https://github.com/llvm/llvm-project/commit/c2d3188d5dcb8158d9b8fa2a85f984fc621c7044
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Port ab380c287a42c0701cd86ae2932c0cb125b9a294
Commit: c9e10034c4f82724dd8ba6f31c1546bf581c90ba
https://github.com/llvm/llvm-project/commit/c9e10034c4f82724dd8ba6f31c1546bf581c90ba
Author: Abhina Sree <69635948+abhina-sree at users.noreply.github.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/include/llvm/Support/AutoConvert.h
Log Message:
-----------
[NFC] Remove dead code (#75336)
Remove dead code
Commit: 6eec80133b2c7b3c22bd665ed8a2fa3928296f36
https://github.com/llvm/llvm-project/commit/6eec80133b2c7b3c22bd665ed8a2fa3928296f36
Author: Piotr Sobczak <piotr.sobczak at amd.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/CodeGen/AMDGPU/fmaximum.ll
A llvm/test/CodeGen/AMDGPU/fmaximum3.ll
A llvm/test/CodeGen/AMDGPU/fminimum.ll
A llvm/test/CodeGen/AMDGPU/fminimum3.ll
A llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
A llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt
Log Message:
-----------
[AMDGPU] Min/max changes for GFX12 (#75214)
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Commit: 9c093cbb5e958beb155e00066fe8982631913e2b
https://github.com/llvm/llvm-project/commit/9c093cbb5e958beb155e00066fe8982631913e2b
Author: Nikita Popov <npopov at redhat.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
M llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
R llvm/test/CodeGen/RISCV/dead-stack-slot.ll
M llvm/test/DebugInfo/COFF/lexicalblock.ll
Log Message:
-----------
Revert "[StackColoring] Delete dead stack slots (#72633)"
This reverts commit a29457844bf0c4b2eb5c0f3877b6e8ef30cdef52.
Causes an assertion failure in llvm/test/DebugInfo/COFF/lexicalblock.ll.
Commit: 79524ba5277555ef58a3eb9c40ed58466a17bcaa
https://github.com/llvm/llvm-project/commit/79524ba5277555ef58a3eb9c40ed58466a17bcaa
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Dialect/ArmSME/enable-arm-streaming.mlir
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir][ArmSME] Add sve streaming compatible attribute (#75222)
Following the same path already used for ArmStreaming and
ArmLocallyStreaming.
This should correspond to clang's __arm_streaming_compatible attribute.
Commit: 7f55d7de1a7511dcfaa37c9f1665bfd8aea5f764
https://github.com/llvm/llvm-project/commit/7f55d7de1a7511dcfaa37c9f1665bfd8aea5f764
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-err.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt
Log Message:
-----------
[AMDGPU] GFX12: Add Split Workgroup Barrier (#74836)
Co-authored-by: Vang Thao <Vang.Thao at amd.com>
Commit: 4b64138ba485fd0fca69613e429e585ee4b67575
https://github.com/llvm/llvm-project/commit/4b64138ba485fd0fca69613e429e585ee4b67575
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
Log Message:
-----------
[DebugInfo][RemoveDIs] Switch some insertion routines to use iterators (#75330)
As part of RemoveDIs, we need instruction insertion to be done with
iterators rather than instruction pointers, so that we can communicate
some debug-info facts about the position. This patch is an entirely
mechanical replacement of Instruction * with BasicBlock::iterator, plus
using insertBefore to insert some instructions because we don't have
iterator-taking constructors yet.
Sadly it's not NFC because it causes dbg.value intrinsics / their
DPValue equivalents to shift location.
Commit: c394d97ed3c10a8a77742296248e68c654f37c45
https://github.com/llvm/llvm-project/commit/c394d97ed3c10a8a77742296248e68c654f37c45
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
A llvm/test/MC/X86/avx-32-att.s
A llvm/test/MC/X86/avx-64-att.s
A llvm/test/MC/X86/avx-64-intel.s
A llvm/test/MC/X86/avx512-att-errors.s
A llvm/test/MC/X86/avx512-att.s
R llvm/test/MC/X86/avx512-encodings.s
R llvm/test/MC/X86/avx512-err.s
A llvm/test/MC/X86/avx512-intel-errors.s
A llvm/test/MC/X86/avx512-intel.s
A llvm/test/MC/X86/avx5124fmaps-att.s
R llvm/test/MC/X86/avx5124fmaps-encoding.s
A llvm/test/MC/X86/avx5124vnniw-att.s
R llvm/test/MC/X86/avx5124vnniw-encoding.s
A llvm/test/MC/X86/avx512bw-64-att.s
A llvm/test/MC/X86/avx512bw-att.s
R llvm/test/MC/X86/avx512bw-encoding.s
A llvm/test/MC/X86/avx512bw_vl-64-att.s
A llvm/test/MC/X86/avx512cd-att.s
A llvm/test/MC/X86/avx512cd_vl-att.s
A llvm/test/MC/X86/avx512dq-att.s
A llvm/test/MC/X86/avx512f_vl-att.s
A llvm/test/MC/X86/avx512f_vl-intel.s
A llvm/test/MC/X86/avx512fp16-att.s
A llvm/test/MC/X86/avx512fp16-intel.s
R llvm/test/MC/X86/avx512fp16.s
A llvm/test/MC/X86/avx512fp16vl-att.s
A llvm/test/MC/X86/avx512fp16vl-intel.s
R llvm/test/MC/X86/avx512fp16vl.s
A llvm/test/MC/X86/avx512gfni-att.s
R llvm/test/MC/X86/avx512gfni-encoding.s
A llvm/test/MC/X86/avx512ifma-att.s
R llvm/test/MC/X86/avx512ifma-encoding.s
A llvm/test/MC/X86/avx512ifmavl-att.s
R llvm/test/MC/X86/avx512ifmavl-encoding.s
A llvm/test/MC/X86/avx512pf-64-att.s
A llvm/test/MC/X86/avx512vaes-att.s
R llvm/test/MC/X86/avx512vaes-encoding.s
A llvm/test/MC/X86/avx512vbmi2-att.s
R llvm/test/MC/X86/avx512vbmi2-encoding.s
A llvm/test/MC/X86/avx512vbmi2vl-att.s
R llvm/test/MC/X86/avx512vbmi2vl-encoding.s
A llvm/test/MC/X86/avx512vbmi_vl-intel.s
A llvm/test/MC/X86/avx512vl-att.s
R llvm/test/MC/X86/avx512vl-encoding.s
A llvm/test/MC/X86/avx512vl_bitalg-att.s
R llvm/test/MC/X86/avx512vl_bitalg-encoding.s
A llvm/test/MC/X86/avx512vl_gfni-att.s
R llvm/test/MC/X86/avx512vl_gfni-encoding.s
A llvm/test/MC/X86/avx512vl_vaes-att.s
R llvm/test/MC/X86/avx512vl_vaes-encoding.s
A llvm/test/MC/X86/avx512vl_vnni-att.s
R llvm/test/MC/X86/avx512vl_vnni-encoding.s
A llvm/test/MC/X86/avx512vnni-att.s
R llvm/test/MC/X86/avx512vnni-encoding.s
A llvm/test/MC/X86/avx512vpopcntdq-64-att.s
A llvm/test/MC/X86/avx_clmul-att.s
A llvm/test/MC/X86/avx_vaes-att.s
R llvm/test/MC/X86/avx_vaes-encoding.s
A llvm/test/MC/X86/avx_vnni-32-intel.s
A llvm/test/MC/X86/avx_vnni-64-att.s
A llvm/test/MC/X86/avx_vnni-64-intel.s
A llvm/test/MC/X86/avx_vnni-att-32.s
R llvm/test/MC/X86/avx_vnni-encoding.s
A llvm/test/MC/X86/bmi-att.s
A llvm/test/MC/X86/cet-att.s
R llvm/test/MC/X86/cet-encoding.s
A llvm/test/MC/X86/fma3-att.s
A llvm/test/MC/X86/fma4-att.s
A llvm/test/MC/X86/gfni-att.s
R llvm/test/MC/X86/gfni-encoding.s
A llvm/test/MC/X86/hle-att.s
R llvm/test/MC/X86/intel-syntax-avx512-error.s
R llvm/test/MC/X86/intel-syntax-avx512.s
R llvm/test/MC/X86/intel-syntax-avx512fp16.s
R llvm/test/MC/X86/intel-syntax-avx512fp16vl.s
R llvm/test/MC/X86/intel-syntax-avx_vnni.s
R llvm/test/MC/X86/intel-syntax-x86-64-avx.s
R llvm/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s
R llvm/test/MC/X86/intel-syntax-x86-64-avx_vnni.s
R llvm/test/MC/X86/intel-syntax-x86-avx512vbmi_vl.s
A llvm/test/MC/X86/lwp-64-att.s
A llvm/test/MC/X86/lwp-att.s
R llvm/test/MC/X86/lwp-x86_64.s
R llvm/test/MC/X86/lwp.s
A llvm/test/MC/X86/msrlist-64-att.s
A llvm/test/MC/X86/rand-att.s
A llvm/test/MC/X86/raoint-64-att.s
A llvm/test/MC/X86/raoint-64-intel.s
A llvm/test/MC/X86/rtm-att.s
A llvm/test/MC/X86/sse4a-att.s
A llvm/test/MC/X86/tbm-att.s
R llvm/test/MC/X86/x86-32-avx.s
R llvm/test/MC/X86/x86-64-avx512bw.s
R llvm/test/MC/X86/x86-64-avx512bw_vl.s
R llvm/test/MC/X86/x86-64-avx512cd.s
R llvm/test/MC/X86/x86-64-avx512cd_vl.s
R llvm/test/MC/X86/x86-64-avx512dq.s
R llvm/test/MC/X86/x86-64-avx512f_vl.s
R llvm/test/MC/X86/x86-64-avx512pf.s
R llvm/test/MC/X86/x86-64-avx512vpopcntdq.s
R llvm/test/MC/X86/x86-64-avx_vnni-encoding.s
R llvm/test/MC/X86/x86-64-msrlist.s
R llvm/test/MC/X86/x86-64-rao-int-att.s
R llvm/test/MC/X86/x86-64-rao-int-intel.s
R llvm/test/MC/X86/x86_64-avx-clmul-encoding.s
R llvm/test/MC/X86/x86_64-avx-encoding.s
R llvm/test/MC/X86/x86_64-bmi-encoding.s
R llvm/test/MC/X86/x86_64-fma3-encoding.s
R llvm/test/MC/X86/x86_64-fma4-encoding.s
R llvm/test/MC/X86/x86_64-hle-encoding.s
R llvm/test/MC/X86/x86_64-rand-encoding.s
R llvm/test/MC/X86/x86_64-rtm-encoding.s
R llvm/test/MC/X86/x86_64-sse4a.s
R llvm/test/MC/X86/x86_64-tbm-encoding.s
R llvm/test/MC/X86/x86_64-xop-encoding.s
A llvm/test/MC/X86/xop-att.s
Log Message:
-----------
[X86][test] Rename some encoding tests
This is the 1st step for D40776, to help us find missing and duplicated
tests.
Commit: a26aa79a3ba5638cd1f8a1a12ae30e481dd2f007
https://github.com/llvm/llvm-project/commit/a26aa79a3ba5638cd1f8a1a12ae30e481dd2f007
Author: Rafael Auler <rafaelauler at fb.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M bolt/test/X86/dwarf-test-df-logging.test
M bolt/test/X86/dwarf4-df-dualcu.test
M bolt/test/X86/dwarf4-split-dwarf-no-address.test
M bolt/test/X86/dwarf5-df-dualcu.test
M bolt/test/X86/dwarf5-df-mono-dualcu.test
M bolt/test/X86/dwarf5-locaddrx.test
Log Message:
-----------
[BOLT] Fix some dwarf tests affected by 75095 (#75327)
PR 75095 introduced some changes to lld that broke some dwarf tests that
were being incorrectly linked as a PIE. Add flags to disable any PIC/PIE
compilation, so the linker can succeed and the tests can run as
intended.
Commit: b81c69415e47bcf59801cb751eed08a6d1cb23f1
https://github.com/llvm/llvm-project/commit/b81c69415e47bcf59801cb751eed08a6d1cb23f1
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M libcxx/include/__chrono/day.h
M libcxx/include/__chrono/hh_mm_ss.h
M libcxx/include/__chrono/month.h
M libcxx/include/__chrono/monthday.h
M libcxx/include/__chrono/weekday.h
M libcxx/include/__chrono/year_month.h
M libcxx/include/__chrono/year_month_day.h
M libcxx/include/__variant/monostate.h
M libcxx/include/cmath
M libcxx/include/complex
M libcxx/include/cstddef
Log Message:
-----------
[libc++][NFC] Add a few explicit 'inline' keywords, mostly in <chrono> (#75234)
Even though constexpr implicitly makes functions inline, we try not to
rely on this implicit effect in the code base. We are mostly consistent
about using `inline` on non-template free-functions to make it clear
that we don't have an ODR violation.
This patch simply fixes a few places where we didn't explicitly use
inline on non-template free functions, presumably because they were
constexpr.
Fixes #75227
Commit: 3564c85b0e3aece63b894fae5c833d261bcfb15f
https://github.com/llvm/llvm-project/commit/3564c85b0e3aece63b894fae5c833d261bcfb15f
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
Log Message:
-----------
[RISCV] Eliminate dead li after emitting VSETVLIs (#65934)
This patch tracks li instructions that set AVL operands and does DCE
after emitting VSETVLIs.
Commit: 26fbdff458ed8a829f732074c06f289b92867a82
https://github.com/llvm/llvm-project/commit/26fbdff458ed8a829f732074c06f289b92867a82
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/debug.ll
M llvm/test/Transforms/ConstraintElimination/reproducer-remarks-debug.ll
Log Message:
-----------
[ConstraintElim] Refactor `checkCondition`. NFC. (#75319)
This patch refactors `checkCondition` to handle min/max intrinsic calls
in #75306.
Commit: 785e0945ce49cf5be0d8fcc0874ad6a5c94fc920
https://github.com/llvm/llvm-project/commit/785e0945ce49cf5be0d8fcc0874ad6a5c94fc920
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/user_defined_char_type.pass.cpp
Log Message:
-----------
[libc++] Fix incomplete user-defined ctype specialization in test (#74630)
The specialization was non-conforming because it was missing a bunch of
member functions. Those were missing probably just as an oversight
coupled with a bit of laziness -- the rule that user-defined
specializations need to match the base template is usually OK to take
with a grain of salt, but not when the code is supposed to be portable,
which our test suite aims to be.
Fixes #74214
Commit: 60aeea21fd885de1e03b354f455b91c47ed0d7e1
https://github.com/llvm/llvm-project/commit/60aeea21fd885de1e03b354f455b91c47ed0d7e1
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Log Message:
-----------
[InstCombine] Fix uninitialized variable usage
m_Specific can only be used if the previous check suceeded. Found by
msan.
Commit: ae2f8167eefbc78c6b6408c9ee3b7c7965ed596a
https://github.com/llvm/llvm-project/commit/ae2f8167eefbc78c6b6408c9ee3b7c7965ed596a
Author: Petr Hosek <phosek at google.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
[CMake] Include opt-viewer in Fuchsia toolchain (#75296)
This is necessary for visualization of optimization remarks.
Commit: 6892c175c565e59cf485ada6b1febd41b4666414
https://github.com/llvm/llvm-project/commit/6892c175c565e59cf485ada6b1febd41b4666414
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
A llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
Log Message:
-----------
AMDGPU/GlobalISel: add AMDGPUGlobalISelDivergenceLowering pass (#75340)
Add empty AMDGPUGlobalISelDivergenceLowering pass. This pass will
implement
- selection of divergent i1 phis as lane mask phis, requires lane mask
merging in some cases
- lower uses of divergent i1 values outside of the cycle using lane mask
merging
- lowering of all cases of temporal divergence:
- lower uses of uniform i1 values outside of the cycle using lane mask
merging
- lower uses of uniform non-i1 values outside of the cycle using a copy
to vgpr inside of the cycle
Add very detailed set of regression tests for cases mentioned above.
patch 1 from: https://github.com/llvm/llvm-project/pull/73337
Commit: f2464ca317bfeeedddb7cbdea3c2c8ec487890bb
https://github.com/llvm/llvm-project/commit/f2464ca317bfeeedddb7cbdea3c2c8ec487890bb
Author: CarolineConcatto <caroline.concatto at arm.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Basic/arm_sve_sme_incl.td
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fp_reduce.c
A clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_int_reduce.c
M clang/utils/TableGen/SveEmitter.cpp
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/sve2p1-intrinsics-fp-reduce.ll
A llvm/test/CodeGen/AArch64/sve2p1-intrinsics-int-reduce.ll
Log Message:
-----------
[SVE2.1][Clang][LLVM]Int/FP reduce builtin in Clang and LLVM intrinsic (#69926)
This patch implements the builtins in Clang
and the LLVM-IR intrinsic for the following:
// Variants are also available for:
// _s8, _s16, _u16, _s32, _u32, _s64, _u64,
// _f16, _f32, _f64uint8x16_t svaddqv[_u8](svbool_t pg, svuint8_t zn);
// Variants are also available for:
// _s8, _u16, _s16, _u32, _s32, _u64, _s64
uint8x16_t svandqv[_u8](svbool_t pg, svuint8_t zn); uint8x16_t
sveorqv[_u8](svbool_t pg, svuint8_t zn); uint8x16_t svorqv[_u8](svbool_t
pg, svuint8_t zn);
// Variants are also available for:
// _s8, _u16, _s16, _u32, _s32, _u64, _s64;
uint8x16_t svmaxqv[_u8](svbool_t pg, svuint8_t zn); uint8x16_t
svminqv[_u8](svbool_t pg, svuint8_t zn);
// Variants are also available for _f32, _f64
float16x8_t svmaxnmqv[_f16](svbool_t pg, svfloat16_t zn); float16x8_t
svminnmqv[_f16](svbool_t pg, svfloat16_t zn);
According to the PR#257[1]
The reduction instruction uses scalable vectors as input and fixed
vectors as output, therefore we changed SVEEmitter to emit fixed vector
types in case the neon header(arm_neon.h) is not present.
[1]https://github.com/ARM-software/acle/pull/257
Co-author: Dinar Temirbulatov <dinar.temirbulatov at arm.com>
Commit: f0ac6f92a77ce2c38f803cf77c5c0a630debd570
https://github.com/llvm/llvm-project/commit/f0ac6f92a77ce2c38f803cf77c5c0a630debd570
Author: Kazu Hirata <kazu at google.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
Log Message:
-----------
[Transforms] Fix a warning
This patch fixes:
llvm/lib/Transforms/Scalar/ConstraintElimination.cpp:1112:13: error:
unused function 'dumpUnpackedICmp' [-Werror,-Wunused-function]
Commit: d87191942dc4701fafd7e87f02305711a4fd22f2
https://github.com/llvm/llvm-project/commit/d87191942dc4701fafd7e87f02305711a4fd22f2
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/cl-options.c
M clang/test/Driver/clang_f_opts.c
Log Message:
-----------
[clang][Driver] Support -fms-volatile as equivalent to /volatile:ms (#74790)
The flag -fms-volatile has existed as a -cc1 flag for a while. It also
technically existed as a driver flag, but didn't do anything because it
wasn't wired up to anything in the driver.
This patch adds -fno-ms-volatile, and makes both -fms-volatile and
-fno-ms-volatile work the same way as the cl-mode flags. The defaults
are unchanged (default on for x86 in cl mode, default off otherwise).
Commit: eaa11526c873b65a9dc0aaf0ebaf66de3db8ed21
https://github.com/llvm/llvm-project/commit/eaa11526c873b65a9dc0aaf0ebaf66de3db8ed21
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M libc/include/llvm-libc-macros/linux/fcntl-macros.h
M libc/include/llvm-libc-macros/linux/sys-stat-macros.h
M libc/src/__support/File/linux/file.cpp
Log Message:
-----------
[libc] fix -Wmacro-redefined (#75261)
When building with compiler-rt enabled, warnings such as the following
are
observed:
llvm-project/llvm/build/projects/compiler-rt/../libc/include/llvm-libc-macros/linux/sys-stat-macros.h:46:9:
warning: 'S_IXOTH' macro redefined [-Wmacro-redefined]
#define S_IXOTH 00001
^
llvm-project/llvm/build/projects/compiler-rt/../libc/include/llvm-libc-macros/linux/fcntl-macros.h:61:9:
note: previous definition is here
#define S_IXOTH 01
^
It looks like we have these multiply defined. Deduplicate these flags;
users
should expect to find them in sys/stat.h. S_FIFO was wrong anyways
(should
have been S_IFIFO).
Commit: f3dcc2351cff7b26c9870d737e5d431551542d9e
https://github.com/llvm/llvm-project/commit/f3dcc2351cff7b26c9870d737e5d431551542d9e
Author: Kazu Hirata <kazu at google.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.h
M clang/lib/APINotes/APINotesManager.cpp
M clang/lib/APINotes/APINotesYAMLCompiler.cpp
M clang/lib/ARCMigrate/ARCMT.cpp
M clang/lib/ARCMigrate/ObjCMT.cpp
M clang/lib/ARCMigrate/TransUnbridgedCasts.cpp
M clang/lib/ARCMigrate/TransformActions.cpp
M clang/lib/ARCMigrate/Transforms.cpp
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/Mangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/AST/PrintfFormatString.cpp
M clang/lib/AST/RawCommentList.cpp
M clang/lib/AST/Stmt.cpp
M clang/lib/ASTMatchers/ASTMatchersInternal.cpp
M clang/lib/ASTMatchers/Dynamic/Parser.cpp
M clang/lib/Analysis/BodyFarm.cpp
M clang/lib/Analysis/CallGraph.cpp
M clang/lib/Analysis/CalledOnceCheck.cpp
M clang/lib/Analysis/CocoaConventions.cpp
M clang/lib/Analysis/FlowSensitive/Models/ChromiumCheckModel.cpp
M clang/lib/Analysis/RetainSummaryManager.cpp
M clang/lib/Basic/Attributes.cpp
M clang/lib/Basic/DiagnosticIDs.cpp
M clang/lib/Basic/IdentifierTable.cpp
M clang/lib/Basic/Module.cpp
M clang/lib/Basic/Sarif.cpp
M clang/lib/Basic/TargetInfo.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/Mips.cpp
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Warnings.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGException.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/CGRecordLayoutBuilder.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/lib/Driver/Distro.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/Job.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/AIX.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/Arch/AArch64.cpp
M clang/lib/Driver/ToolChains/Arch/ARM.cpp
M clang/lib/Driver/ToolChains/Arch/X86.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Driver/ToolChains/Hurd.cpp
M clang/lib/Driver/ToolChains/MSP430.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Driver/ToolChains/PPCLinux.cpp
M clang/lib/Driver/ToolChains/Solaris.cpp
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/lib/Edit/Commit.cpp
M clang/lib/Edit/RewriteObjCFoundationAPI.cpp
M clang/lib/ExtractAPI/ExtractAPIConsumer.cpp
M clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp
M clang/lib/Format/BreakableToken.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/SortJavaScriptImports.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/DependencyGraph.cpp
M clang/lib/Frontend/Rewrite/InclusionRewriter.cpp
M clang/lib/Frontend/VerifyDiagnosticConsumer.cpp
M clang/lib/Index/IndexSymbol.cpp
M clang/lib/IndexSerialization/SerializablePathCollection.cpp
M clang/lib/Lex/HeaderSearch.cpp
M clang/lib/Lex/InitHeaderSearch.cpp
M clang/lib/Lex/Lexer.cpp
M clang/lib/Lex/ModuleMap.cpp
M clang/lib/Lex/PPDirectives.cpp
M clang/lib/Lex/PPExpressions.cpp
M clang/lib/Lex/PPMacroExpansion.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Rewrite/Rewriter.cpp
M clang/lib/Sema/CodeCompleteConsumer.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaCodeComplete.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclObjC.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaModule.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/StaticAnalyzer/Checkers/CheckObjCDealloc.cpp
M clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp
M clang/lib/StaticAnalyzer/Checkers/DeadStoresChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/GCDAntipatternChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/ObjCPropertyChecker.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp
M clang/lib/StaticAnalyzer/Core/CallEvent.cpp
M clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
M clang/lib/StaticAnalyzer/Core/CheckerRegistryData.cpp
M clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp
M clang/lib/StaticAnalyzer/Frontend/CheckerRegistry.cpp
M clang/lib/Support/RISCVVIntrinsicUtils.cpp
M clang/lib/Tooling/ASTDiff/ASTDiff.cpp
M clang/lib/Tooling/ArgumentsAdjusters.cpp
M clang/lib/Tooling/CompilationDatabase.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningFilesystem.cpp
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
M clang/lib/Tooling/Inclusions/HeaderAnalysis.cpp
M clang/lib/Tooling/Inclusions/HeaderIncludes.cpp
M clang/lib/Tooling/Refactoring/AtomicChange.cpp
M clang/lib/Tooling/Refactoring/Lookup.cpp
M clang/lib/Tooling/Refactoring/Rename/USRLocFinder.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/lib/Tooling/Transformer/SourceCode.cpp
M clang/tools/arcmt-test/arcmt-test.cpp
M clang/tools/clang-extdef-mapping/ClangExtDefMapGen.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-refactor/ClangRefactor.cpp
M clang/tools/clang-repl/ClangRepl.cpp
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/diagtool/TreeView.cpp
M clang/tools/driver/driver.cpp
M clang/tools/libclang/CIndexUSRs.cpp
M clang/unittests/Analysis/CloneDetectionTest.cpp
M clang/unittests/Driver/ModuleCacheTest.cpp
M clang/unittests/Driver/MultilibBuilderTest.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/unittests/Frontend/OutputStreamTest.cpp
M clang/unittests/Interpreter/IncrementalProcessingTest.cpp
M clang/unittests/StaticAnalyzer/AnalyzerOptionsTest.cpp
M clang/unittests/Tooling/HeaderIncludesTest.cpp
M clang/unittests/libclang/LibclangTest.cpp
M clang/utils/TableGen/ASTTableGen.cpp
M clang/utils/TableGen/MveEmitter.cpp
Log Message:
-----------
[clang] Use StringRef::{starts,ends}_with (NFC) (#75149)
This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::{starts,ends}_with in C++20.
I'm planning to deprecate and eventually remove
StringRef::{starts,ends}with.
Commit: 6b37d8b73fcfec0619465d9d526046fa5f8210fe
https://github.com/llvm/llvm-project/commit/6b37d8b73fcfec0619465d9d526046fa5f8210fe
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M libc/test/src/math/FDimTest.h
M libc/test/src/math/FmaTest.h
M libc/test/src/math/ILogbTest.h
M libc/test/src/math/LdExpTest.h
M libc/test/src/math/RemQuoTest.h
M libc/test/src/math/smoke/FDimTest.h
M libc/test/src/math/smoke/FmaTest.h
M libc/test/src/math/smoke/ILogbTest.h
M libc/test/src/math/smoke/LdExpTest.h
M libc/test/src/math/smoke/RemQuoTest.h
Log Message:
-----------
[libc][NFC] Shorten type names in tests (#75358)
Commit: 74818511b6380d51bbbb2045da5b774d44c88041
https://github.com/llvm/llvm-project/commit/74818511b6380d51bbbb2045da5b774d44c88041
Author: eric <eric at efcs.ca>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M libcxx/docs/index.rst
Log Message:
-----------
Move status badge as suggested in post-commit review
Commit: 8d7c9798153fbaa285f73585a1d87c8d00de0030
https://github.com/llvm/llvm-project/commit/8d7c9798153fbaa285f73585a1d87c8d00de0030
Author: Bharathi Ramana Joshi <joshibharathiramana at gmail.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M mlir/lib/Analysis/Presburger/IntegerRelation.cpp
M mlir/unittests/Analysis/Presburger/IntegerRelationTest.cpp
Log Message:
-----------
[MLIR][Presburger] Fix IntegerRelation::swapVar not swapping identifiers (#74407)
This commit fixes a bug where identifiers were not swapped when doing a
IntegerRelation::swapVar.
Commit: 930b5b52ffe699dbcf05eea32d12a2861dd2bdf6
https://github.com/llvm/llvm-project/commit/930b5b52ffe699dbcf05eea32d12a2861dd2bdf6
Author: Paul Walker <paul.walker at arm.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
M llvm/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll
Log Message:
-----------
[ConstantHoisting] Add a TTI hook to prevent hoisting. (#69004)
Code generation can sometimes simplify expensive operations when
an operand is constant. An example of this is divides on AArch64
where they can be rewritten using a cheaper sequence of multiplies
and subtracts. Doing this is often better than hoisting expensive
constants which are likely to be hoisted by MachineLICM anyway.
Commit: 5540d81bf3728cfb8cf2c25270b4a814e09d9143
https://github.com/llvm/llvm-project/commit/5540d81bf3728cfb8cf2c25270b4a814e09d9143
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Manually port ed2d497291f
Commit: 2c185709bca195f3d5e062819bba5dd828330548
https://github.com/llvm/llvm-project/commit/2c185709bca195f3d5e062819bba5dd828330548
Author: Craig Topper <craig.topper at sifive.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/double-previous-failure.ll
M llvm/test/CodeGen/RISCV/select-and.ll
M llvm/test/CodeGen/RISCV/select-or.ll
M llvm/test/CodeGen/RISCV/setcc-logic.ll
M llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
Log Message:
-----------
[RISCV] Remove setJumpIsExpensive(). (#74647)
Middle end up optimizations can speculate away the short circuit
behavior of C/C++ && and ||. Using i1 and/or or logical select
instructions and a single branch.
SelectionDAGBuilder can turn i1 and/or/select back into multiple
branches, but this is disabled when jump is expensive.
RISC-V can use slt(u)(i) to evaluate a condition into any GPR which
makes us better than other targets that use a flag register. RISC-V also
has single instruction compare and branch. So its not clear from a code
size perspective that using compare+and/or is better.
If the full condition is dependent on multiple loads, using a logic
delays the branch resolution until all the loads are resolved even if
there is a cheap condition that makes the loads unnecessary.
PowerPC and Lanai are the only CPU targets that use setJumpIsExpensive.
NVPTX and AMDGPU also use it but they are GPU targets. PowerPC appears
to have a MachineIR pass that turns AND/OR of CR bits into multiple
branches. I don't know anything about Lanai and their reason for using
setJumpIsExpensive.
I think the decision to use logic vs branches is much more nuanced than
this big hammer. So I propose to make RISC-V match other CPU targets.
Anyone who wants the old behavior can still pass -mllvm
-jump-is-expensive=true.
Commit: 12f6d556d22e2b3a170d92f648b231d2a1cb99fd
https://github.com/llvm/llvm-project/commit/12f6d556d22e2b3a170d92f648b231d2a1cb99fd
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 6892c175c565
Commit: 2c5fe1486c36203e78daee6be571145a5d6084e2
https://github.com/llvm/llvm-project/commit/2c5fe1486c36203e78daee6be571145a5d6084e2
Author: Maksim Panchenko <maks at fb.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M libcxxabi/test/native/x86_64/lpstart-zero.pass.sh.s
Log Message:
-----------
[libc++abi] Fix test on Android (#74753)
Follow up to #72727. The added test could not be executed on Android.
Commit: c0ad6e2fa6353d06aa62b4874f48d5ba2159de56
https://github.com/llvm/llvm-project/commit/c0ad6e2fa6353d06aa62b4874f48d5ba2159de56
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M libc/test/src/fcntl/creat_test.cpp
M libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp
M libc/test/src/unistd/access_test.cpp
M libc/test/src/unistd/dup2_test.cpp
M libc/test/src/unistd/dup3_test.cpp
M libc/test/src/unistd/dup_test.cpp
M libc/test/src/unistd/ftruncate_test.cpp
M libc/test/src/unistd/isatty_test.cpp
M libc/test/src/unistd/link_test.cpp
M libc/test/src/unistd/linkat_test.cpp
M libc/test/src/unistd/pread_pwrite_test.cpp
M libc/test/src/unistd/read_write_test.cpp
M libc/test/src/unistd/symlink_test.cpp
M libc/test/src/unistd/symlinkat_test.cpp
M libc/test/src/unistd/syscall_test.cpp
M libc/test/src/unistd/truncate_test.cpp
M libc/test/src/unistd/unlink_test.cpp
M libc/test/src/unistd/unlinkat_test.cpp
Log Message:
-----------
[libc] fix unit tests (#75361)
Fixes #75261
Commit: ec41462d7a7d2fcd74dcf1c60218f134fcfd55b2
https://github.com/llvm/llvm-project/commit/ec41462d7a7d2fcd74dcf1c60218f134fcfd55b2
Author: Abhina Sree <69635948+abhina-sree at users.noreply.github.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M clang/lib/Lex/HeaderMap.cpp
M llvm/include/llvm/Support/SystemZ/zOSSupport.h
M llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp
M llvm/lib/ObjCopy/MachO/MachOObject.cpp
M llvm/lib/ObjCopy/MachO/MachOReader.cpp
M llvm/lib/ObjectYAML/MachOEmitter.cpp
M llvm/lib/ObjectYAML/MachOYAML.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/tools/llvm-exegesis/lib/Error.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/llvm-readobj/ObjDumper.cpp
M llvm/tools/obj2yaml/macho2yaml.cpp
Log Message:
-----------
[SystemZ][z/OS] Add missing strnlen function for z/OS to fix build failures (#75339)
This patch adds strnlen to the zOSSupport.h file to fix build failures in multiple files.
Commit: 1220edc6e00718181131e1ce57f7225595f39dea
https://github.com/llvm/llvm-project/commit/1220edc6e00718181131e1ce57f7225595f39dea
Author: vdonaldson <37090318+vdonaldson at users.noreply.github.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M flang/lib/Lower/IO.cpp
M flang/test/Lower/namelist.f90
Log Message:
-----------
[flang] module namelist IO with renaming (#75264)
The test:
```
module mmm
real rrr
namelist /aaa/ rrr
end
use mmm, bbb => aaa
rrr = 3.
write(*,bbb)
end
```
Should output: &AAA RRR= 3./
not: &BBB RRR= 3./
Commit: 6d18951b833b2a2dabe268b3be0163e03a9e1142
https://github.com/llvm/llvm-project/commit/6d18951b833b2a2dabe268b3be0163e03a9e1142
Author: Ian Anderson <iana at apple.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M clang/include/clang/Basic/Features.def
M clang/test/Driver/darwin-builtin-modules.c
Log Message:
-----------
Remove the builtin_headers_in_system_modules feature (#75262)
__has_feature(builtin_headers_in_system_modules) was added in
https://reviews.llvm.org/D159483 to be used in the stdarg/stddef
implementation headers. It ended up being unnecessary, but I forgot to
remove the feature definition.
Commit: a5ffabce98a4b2e9d69009fa3e60f2b154100860
https://github.com/llvm/llvm-project/commit/a5ffabce98a4b2e9d69009fa3e60f2b154100860
Author: criis <christian.riis at gmail.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/include/llvm/Support/raw_ostream.h
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Support/raw_ostream.cpp
M llvm/unittests/Support/CMakeLists.txt
A llvm/unittests/Support/raw_socket_stream_test.cpp
Log Message:
-----------
[llvm][Support] Add UNIX socket support (#73603)
This adds support for UNIX socket communication to work similarly to
raw_stream.
---------
Patch by Christian Riis
Commit: c6ecbcb48b9569e6938f4382c67e4b9ac1bf3bdd
https://github.com/llvm/llvm-project/commit/c6ecbcb48b9569e6938f4382c67e4b9ac1bf3bdd
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
Log Message:
-----------
[AMDGPU] Fix no waitcnt produced between LDS DMA and ds_read on gfx10 (#75245)
BUFFER_LOAD_DWORD_LDS was incorrectly touching vscnt instead of the
vmcnt. This is VMEM load and DS store, so it shall use vmcnt.
Commit: 2fd7657b6609454af7adb75765d164ec7d1bb80b
https://github.com/llvm/llvm-project/commit/2fd7657b6609454af7adb75765d164ec7d1bb80b
Author: stephenpeckham <118857872+stephenpeckham at users.noreply.github.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M lld/test/ELF/ppc32-reloc-addr.s
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/test/MC/Disassembler/PowerPC/ppc64-operands.txt
M llvm/test/MC/PowerPC/ppc32-ba.s
M llvm/test/MC/PowerPC/ppc64-operands.s
A llvm/test/tools/llvm-objdump/XCOFF/disassemble-abs.test
Log Message:
-----------
[XCOFF] Display branch-absolute targets in hex. (#72532)
Branch-absolute instructions are currently printed in decimal, and
negative addresses are printed as positive numbers.
With this change, addresses are printed in hex and negative addresses
are converted to an unsigned 32- or 64-bit address.
Commit: a4336f2ec1747ea234a07d683930683f67fbd655
https://github.com/llvm/llvm-project/commit/a4336f2ec1747ea234a07d683930683f67fbd655
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M libcxx/CMakeLists.txt
M libcxx/cmake/config-ix.cmake
M libcxxabi/cmake/config-ix.cmake
M libcxxabi/src/CMakeLists.txt
M libunwind/cmake/config-ix.cmake
Log Message:
-----------
[runtimes] Don't link against compiler-rt explicitly when we use -nostdlib++ (#75089)
When we use the -nostdlib++ flag, we don't need to explicitly link
against compiler-rt, since the compiler already links against it by
default. This simplifies the flags that we need to use when building
with Clang and GCC, and opens the door to further simplifications since
most platforms won't need to detect whether libgcc and libgcc_s are
supported anymore.
Furthermore, on platforms where -nostdlib++ is used, this patch prevents
manually linking compiler-rt *before* other system libraries. For
example, Apple platforms have several compiler-rt symbols defined in
libSystem.dylib. If we manually link against compiler-rt, we end up
overriding the default link order preferred by the compiler and
potentially using the symbols from the clang-provided libclang_rt.a
library instead of the system provided one.
Note that we don't touch how libunwind links against compiler-rt when it
builds the .so/.a because libunwind currently doesn't use -nodefaultlibs
and we want to avoid rocking the boat too much.
rdar://119506163
Commit: 0b46606ca5b52aa515c5359ed6f24fb18d825b50
https://github.com/llvm/llvm-project/commit/0b46606ca5b52aa515c5359ed6f24fb18d825b50
Author: Jakub Mazurkiewicz <mazkuba3 at gmail.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M libcxx/include/__ranges/take_view.h
A libcxx/test/std/ranges/range.adaptors/range.take/range.take.sentinel/base.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.take/range.take.sentinel/ctor.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.take/range.take.sentinel/eq.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.take/sentinel/base.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.take/sentinel/ctor.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.take/sentinel/eq.pass.cpp
M libcxx/test/support/test_comparisons.h
Log Message:
-----------
[libc++] Fix `take_view::__sentinel`'s `operator==` (#74655)
* Fix `take_view::__sentinel`'s `operator==`
* Rename `ranges/range.adaptors/range.take/sentinel/base.pass.cpp`
directory to
`ranges/range.adaptors/range.take/range.take.sentinel/base.pass.cpp`
* Add ***full*** test coverage for `take_view::__sentinel`'s
`operator==`
* Drive-by: fix comment in `base.pass.cpp` test
* Close #55211
Commit: 4805acd4db42921d94058fbefcf8298f0b8b1845
https://github.com/llvm/llvm-project/commit/4805acd4db42921d94058fbefcf8298f0b8b1845
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M compiler-rt/test/sanitizer_common/TestCases/Posix/fork_threaded.c
Log Message:
-----------
[test][sanitizer] Disable test on Darwin
Because it does not implemented pthread_barrier_t.
Commit: 6cad4c91edbc9f9dca3e47255ad341c2d7a714b1
https://github.com/llvm/llvm-project/commit/6cad4c91edbc9f9dca3e47255ad341c2d7a714b1
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
Log Message:
-----------
[gn build] Port a5ffabce98a4
Commit: 64fa90bf8966cb886463840e5c85b9602cbbdc52
https://github.com/llvm/llvm-project/commit/64fa90bf8966cb886463840e5c85b9602cbbdc52
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M compiler-rt/include/sanitizer/hwasan_interface.h
M compiler-rt/lib/hwasan/hwasan.cpp
M compiler-rt/lib/hwasan/hwasan.h
M compiler-rt/lib/hwasan/hwasan_interface_internal.h
A compiler-rt/test/hwasan/TestCases/tag-ptr.cpp
Log Message:
-----------
[hwasan] Add `__hwasan_get_tag_from_pointer` (#75267)
This simplifies handling tags by user code. Now code does not need
to know bit size of tag and its position.
Commit: 7b95f93b998aac4ef218ccacbfa52860f98384cd
https://github.com/llvm/llvm-project/commit/7b95f93b998aac4ef218ccacbfa52860f98384cd
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2023-12-13 (Wed, 13 Dec 2023)
Changed paths:
M bolt/test/X86/dwarf-test-df-logging.test
M bolt/test/X86/dwarf4-df-dualcu.test
M bolt/test/X86/dwarf4-split-dwarf-no-address.test
M bolt/test/X86/dwarf5-df-dualcu.test
M bolt/test/X86/dwarf5-df-mono-dualcu.test
M bolt/test/X86/dwarf5-locaddrx.test
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/Features.def
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Basic/arm_sve_sme_incl.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.h
M clang/lib/APINotes/APINotesManager.cpp
M clang/lib/APINotes/APINotesYAMLCompiler.cpp
M clang/lib/ARCMigrate/ARCMT.cpp
M clang/lib/ARCMigrate/ObjCMT.cpp
M clang/lib/ARCMigrate/TransUnbridgedCasts.cpp
M clang/lib/ARCMigrate/TransformActions.cpp
M clang/lib/ARCMigrate/Transforms.cpp
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/Interp/Interp.cpp
M clang/lib/AST/Mangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/AST/PrintfFormatString.cpp
M clang/lib/AST/RawCommentList.cpp
M clang/lib/AST/Stmt.cpp
M clang/lib/ASTMatchers/ASTMatchersInternal.cpp
M clang/lib/ASTMatchers/Dynamic/Parser.cpp
M clang/lib/Analysis/BodyFarm.cpp
M clang/lib/Analysis/CallGraph.cpp
M clang/lib/Analysis/CalledOnceCheck.cpp
M clang/lib/Analysis/CocoaConventions.cpp
M clang/lib/Analysis/FlowSensitive/Models/ChromiumCheckModel.cpp
M clang/lib/Analysis/RetainSummaryManager.cpp
M clang/lib/Basic/Attributes.cpp
M clang/lib/Basic/DiagnosticIDs.cpp
M clang/lib/Basic/IdentifierTable.cpp
M clang/lib/Basic/Module.cpp
M clang/lib/Basic/Sarif.cpp
M clang/lib/Basic/TargetInfo.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/Mips.cpp
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Warnings.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGException.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/CGRecordLayoutBuilder.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/lib/Driver/Distro.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/Job.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/AIX.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/Arch/AArch64.cpp
M clang/lib/Driver/ToolChains/Arch/ARM.cpp
M clang/lib/Driver/ToolChains/Arch/X86.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Driver/ToolChains/Hurd.cpp
M clang/lib/Driver/ToolChains/MSP430.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Driver/ToolChains/PPCLinux.cpp
M clang/lib/Driver/ToolChains/Solaris.cpp
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/lib/Edit/Commit.cpp
M clang/lib/Edit/RewriteObjCFoundationAPI.cpp
M clang/lib/ExtractAPI/ExtractAPIConsumer.cpp
M clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp
M clang/lib/Format/BreakableToken.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/SortJavaScriptImports.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/DependencyGraph.cpp
M clang/lib/Frontend/Rewrite/InclusionRewriter.cpp
M clang/lib/Frontend/VerifyDiagnosticConsumer.cpp
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Index/IndexSymbol.cpp
M clang/lib/IndexSerialization/SerializablePathCollection.cpp
M clang/lib/Lex/HeaderMap.cpp
M clang/lib/Lex/HeaderSearch.cpp
M clang/lib/Lex/InitHeaderSearch.cpp
M clang/lib/Lex/Lexer.cpp
M clang/lib/Lex/ModuleMap.cpp
M clang/lib/Lex/PPDirectives.cpp
M clang/lib/Lex/PPExpressions.cpp
M clang/lib/Lex/PPMacroExpansion.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Rewrite/Rewriter.cpp
M clang/lib/Sema/CodeCompleteConsumer.cpp
M clang/lib/Sema/SemaCXXScopeSpec.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaCodeComplete.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclObjC.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaModule.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/StaticAnalyzer/Checkers/CheckObjCDealloc.cpp
M clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp
M clang/lib/StaticAnalyzer/Checkers/DeadStoresChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/GCDAntipatternChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/ObjCPropertyChecker.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp
M clang/lib/StaticAnalyzer/Core/CallEvent.cpp
M clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
M clang/lib/StaticAnalyzer/Core/CheckerRegistryData.cpp
M clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp
M clang/lib/StaticAnalyzer/Frontend/CheckerRegistry.cpp
M clang/lib/Support/RISCVVIntrinsicUtils.cpp
M clang/lib/Tooling/ASTDiff/ASTDiff.cpp
M clang/lib/Tooling/ArgumentsAdjusters.cpp
M clang/lib/Tooling/CompilationDatabase.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningFilesystem.cpp
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
M clang/lib/Tooling/Inclusions/HeaderAnalysis.cpp
M clang/lib/Tooling/Inclusions/HeaderIncludes.cpp
M clang/lib/Tooling/Refactoring/AtomicChange.cpp
M clang/lib/Tooling/Refactoring/Lookup.cpp
M clang/lib/Tooling/Refactoring/Rename/USRLocFinder.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/lib/Tooling/Transformer/SourceCode.cpp
M clang/test/AST/Interp/functions.cpp
M clang/test/CXX/temp/temp.decls/temp.alias/p3.cpp
A clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fp_reduce.c
A clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_int_reduce.c
A clang/test/CodeGen/arm-vector_type-params-returns.c
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-err.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M clang/test/Driver/cl-options.c
M clang/test/Driver/clang_f_opts.c
M clang/test/Driver/darwin-builtin-modules.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Sema/aarch64-sve-intrinsics/acle_sve_target.cpp
M clang/test/Sema/arm-vector-types-support.c
M clang/test/Sema/missing-field-initializers.c
M clang/test/SemaCUDA/neon-attrs.cu
M clang/test/SemaCXX/alias-template.cpp
M clang/test/SemaCXX/cxx2a-initializer-aggregates.cpp
M clang/tools/arcmt-test/arcmt-test.cpp
M clang/tools/c-arcmt-test/c-arcmt-test.c
M clang/tools/c-index-test/c-index-test.c
M clang/tools/clang-extdef-mapping/ClangExtDefMapGen.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-refactor/ClangRefactor.cpp
M clang/tools/clang-repl/ClangRepl.cpp
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/diagtool/TreeView.cpp
M clang/tools/driver/driver.cpp
M clang/tools/libclang/CIndexUSRs.cpp
M clang/unittests/Analysis/CloneDetectionTest.cpp
M clang/unittests/Driver/ModuleCacheTest.cpp
M clang/unittests/Driver/MultilibBuilderTest.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/unittests/Frontend/OutputStreamTest.cpp
M clang/unittests/Interpreter/IncrementalProcessingTest.cpp
M clang/unittests/StaticAnalyzer/AnalyzerOptionsTest.cpp
M clang/unittests/Tooling/HeaderIncludesTest.cpp
M clang/unittests/libclang/LibclangTest.cpp
M clang/utils/TableGen/ASTTableGen.cpp
M clang/utils/TableGen/MveEmitter.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
M compiler-rt/test/sanitizer_common/TestCases/Posix/fork_threaded.c
M compiler-rt/test/sanitizer_common/sanitizer_specific.h
M flang/lib/Lower/IO.cpp
M flang/test/Lower/namelist.f90
M libc/include/llvm-libc-macros/linux/fcntl-macros.h
M libc/include/llvm-libc-macros/linux/sys-stat-macros.h
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/generic/FMod.h
M libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
M libc/src/__support/File/linux/file.cpp
M libc/src/__support/str_to_float.h
M libc/src/math/generic/acoshf.cpp
M libc/src/math/generic/asinhf.cpp
M libc/src/math/generic/atanhf.cpp
M libc/src/math/generic/erff.cpp
M libc/src/math/generic/explogxf.h
M libc/src/math/generic/inv_trigf_utils.h
M libc/src/math/generic/log1p.cpp
M libc/src/math/generic/sinhf.cpp
M libc/src/math/generic/tanhf.cpp
M libc/src/stdlib/CMakeLists.txt
M libc/test/src/fcntl/creat_test.cpp
M libc/test/src/math/FDimTest.h
M libc/test/src/math/FmaTest.h
M libc/test/src/math/ILogbTest.h
M libc/test/src/math/LdExpTest.h
M libc/test/src/math/RemQuoTest.h
M libc/test/src/math/smoke/FDimTest.h
M libc/test/src/math/smoke/FmaTest.h
M libc/test/src/math/smoke/ILogbTest.h
M libc/test/src/math/smoke/LdExpTest.h
M libc/test/src/math/smoke/RemQuoTest.h
M libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp
M libc/test/src/unistd/access_test.cpp
M libc/test/src/unistd/dup2_test.cpp
M libc/test/src/unistd/dup3_test.cpp
M libc/test/src/unistd/dup_test.cpp
M libc/test/src/unistd/ftruncate_test.cpp
M libc/test/src/unistd/isatty_test.cpp
M libc/test/src/unistd/link_test.cpp
M libc/test/src/unistd/linkat_test.cpp
M libc/test/src/unistd/pread_pwrite_test.cpp
M libc/test/src/unistd/read_write_test.cpp
M libc/test/src/unistd/symlink_test.cpp
M libc/test/src/unistd/symlinkat_test.cpp
M libc/test/src/unistd/syscall_test.cpp
M libc/test/src/unistd/truncate_test.cpp
M libc/test/src/unistd/unlink_test.cpp
M libc/test/src/unistd/unlinkat_test.cpp
M libcxx/CMakeLists.txt
M libcxx/cmake/config-ix.cmake
M libcxx/docs/index.rst
M libcxx/include/__chrono/day.h
M libcxx/include/__chrono/hh_mm_ss.h
M libcxx/include/__chrono/month.h
M libcxx/include/__chrono/monthday.h
M libcxx/include/__chrono/weekday.h
M libcxx/include/__chrono/year_month.h
M libcxx/include/__chrono/year_month_day.h
M libcxx/include/__ranges/lazy_split_view.h
M libcxx/include/__ranges/split_view.h
M libcxx/include/__ranges/take_view.h
M libcxx/include/__variant/monostate.h
M libcxx/include/cmath
M libcxx/include/complex
M libcxx/include/cstddef
M libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/user_defined_char_type.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.lazy.split/adaptor.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.split/adaptor.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.take/range.take.sentinel/base.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.take/range.take.sentinel/ctor.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.take/range.take.sentinel/eq.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.take/sentinel/base.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.take/sentinel/ctor.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.take/sentinel/eq.pass.cpp
M libcxx/test/support/test_comparisons.h
M libcxxabi/cmake/config-ix.cmake
M libcxxabi/src/CMakeLists.txt
M libcxxabi/test/native/x86_64/lpstart-zero.pass.sh.s
M libunwind/cmake/config-ix.cmake
M lld/COFF/Driver.cpp
M lld/test/COFF/Inputs/loadconfig-arm64ec.s
M lld/test/COFF/Inputs/loadconfig-cfg-x64.s
A lld/test/COFF/merge-00cfg.s
M lld/test/ELF/ppc32-reloc-addr.s
M lldb/test/API/lang/cpp/union-static-data-members/TestCppUnionStaticMembers.py
R lldb/test/API/python_api/global_module_cache/Makefile
R lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py
R lldb/test/API/python_api/global_module_cache/one-print.c
R lldb/test/API/python_api/global_module_cache/two-print.c
M lldb/unittests/SymbolFile/PDB/SymbolFilePDBTests.cpp
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/TableGen/index.rst
M llvm/include/llvm/Analysis/AliasSetTracker.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
A llvm/include/llvm/CodeGen/ExpandMemCmp.h
M llvm/include/llvm/CodeGen/GCMetadata.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
A llvm/include/llvm/CodeGen/IndirectBrExpand.h
M llvm/include/llvm/CodeGen/MachinePassRegistry.def
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/LinkAllPasses.h
M llvm/include/llvm/MC/MCFragment.h
M llvm/include/llvm/Support/AMDHSAKernelDescriptor.h
M llvm/include/llvm/Support/AutoConvert.h
M llvm/include/llvm/Support/SystemZ/zOSSupport.h
M llvm/include/llvm/Support/raw_ostream.h
M llvm/lib/Analysis/AliasSetTracker.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/ExpandMemCmp.cpp
M llvm/lib/CodeGen/GCMetadata.cpp
M llvm/lib/CodeGen/IndirectBrExpandPass.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp
M llvm/lib/ObjCopy/MachO/MachOObject.cpp
M llvm/lib/ObjCopy/MachO/MachOReader.cpp
M llvm/lib/ObjectYAML/MachOEmitter.cpp
M llvm/lib/ObjectYAML/MachOYAML.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Support/AutoConvert.cpp
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Support/InitLLVM.cpp
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Support/Unix/Program.inc
M llvm/lib/Support/raw_ostream.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
A llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.cpp
M llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.h
M llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.h
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Coroutines/CoroInternal.h
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp
M llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
M llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
M llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll
A llvm/test/CodeGen/AArch64/sink-and-fold-clear-kill-flags.mir
A llvm/test/CodeGen/AArch64/sve2p1-intrinsics-fp-reduce.ll
A llvm/test/CodeGen/AArch64/sve2p1-intrinsics-int-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
A llvm/test/CodeGen/AMDGPU/fmaximum.ll
A llvm/test/CodeGen/AMDGPU/fmaximum3.ll
A llvm/test/CodeGen/AMDGPU/fminimum.ll
A llvm/test/CodeGen/AMDGPU/fminimum3.ll
A llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
A llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/double-previous-failure.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/select-and.ll
M llvm/test/CodeGen/RISCV/select-or.ll
M llvm/test/CodeGen/RISCV/setcc-logic.ll
M llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
A llvm/test/CodeGen/X86/coalescer-dead-flag-verifier-error.ll
A llvm/test/CodeGen/X86/coalescer-partial-redundancy-clear-dead-flag-undef-copy.mir
A llvm/test/CodeGen/X86/coalescer-remat-with-undef-implicit-def-operand.mir
M llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s
A llvm/test/MC/AMDGPU/hsa-gfx12-v4.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64-operands.txt
A llvm/test/MC/Disassembler/X86/avx512_bf16-32.txt
A llvm/test/MC/Disassembler/X86/avx512_bf16-64.txt
A llvm/test/MC/Disassembler/X86/avx512_bf16_vl-32.txt
A llvm/test/MC/Disassembler/X86/avx512_bf16_vl-64.txt
R llvm/test/MC/Disassembler/X86/avx512bf16-att.txt
R llvm/test/MC/Disassembler/X86/avx512bf16-intel.txt
R llvm/test/MC/Disassembler/X86/avx512bf16vl-att.txt
R llvm/test/MC/Disassembler/X86/avx512bf16vl-intel.txt
A llvm/test/MC/Disassembler/X86/avx512bitalg.txt
A llvm/test/MC/Disassembler/X86/avx512dq_vl.txt
A llvm/test/MC/Disassembler/X86/avx512vbmi.txt
A llvm/test/MC/Disassembler/X86/avx512vp2intersect-32.txt
A llvm/test/MC/Disassembler/X86/avx512vp2intersect-64.txt
A llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-32.txt
A llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-64.txt
R llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-att.txt
R llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-intel.txt
R llvm/test/MC/Disassembler/X86/x86-64-avx512bf16-att.txt
R llvm/test/MC/Disassembler/X86/x86-64-avx512bf16-intel.txt
R llvm/test/MC/Disassembler/X86/x86-64-avx512bf16vl-att.txt
R llvm/test/MC/Disassembler/X86/x86-64-avx512bf16vl-intel.txt
R llvm/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-att.txt
R llvm/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-intel.txt
M llvm/test/MC/PowerPC/ppc32-ba.s
M llvm/test/MC/PowerPC/ppc64-operands.s
M llvm/test/MC/RISCV/attribute-arch.s
A llvm/test/MC/X86/avx-32-att.s
A llvm/test/MC/X86/avx-64-att.s
A llvm/test/MC/X86/avx-64-intel.s
A llvm/test/MC/X86/avx512-att-errors.s
A llvm/test/MC/X86/avx512-att.s
R llvm/test/MC/X86/avx512-encodings.s
R llvm/test/MC/X86/avx512-err.s
A llvm/test/MC/X86/avx512-intel-errors.s
A llvm/test/MC/X86/avx512-intel.s
A llvm/test/MC/X86/avx5124fmaps-att.s
R llvm/test/MC/X86/avx5124fmaps-encoding.s
A llvm/test/MC/X86/avx5124vnniw-att.s
R llvm/test/MC/X86/avx5124vnniw-encoding.s
A llvm/test/MC/X86/avx512_bf16-32-att.s
A llvm/test/MC/X86/avx512_bf16-32-intel.s
A llvm/test/MC/X86/avx512_bf16-64-att.s
A llvm/test/MC/X86/avx512_bf16-64-intel.s
R llvm/test/MC/X86/avx512_bf16-encoding.s
A llvm/test/MC/X86/avx512_bf16_vl-32-att.s
A llvm/test/MC/X86/avx512_bf16_vl-32-intel.s
A llvm/test/MC/X86/avx512_bf16_vl-64-att.s
A llvm/test/MC/X86/avx512_bf16_vl-64-intel.s
R llvm/test/MC/X86/avx512_bf16_vl-encoding.s
A llvm/test/MC/X86/avx512bitalg-att.s
R llvm/test/MC/X86/avx512bitalg-encoding.s
A llvm/test/MC/X86/avx512bitalg-intel.s
A llvm/test/MC/X86/avx512bw-64-att.s
A llvm/test/MC/X86/avx512bw-att.s
R llvm/test/MC/X86/avx512bw-encoding.s
A llvm/test/MC/X86/avx512bw_vl-64-att.s
A llvm/test/MC/X86/avx512cd-att.s
A llvm/test/MC/X86/avx512cd_vl-att.s
A llvm/test/MC/X86/avx512dq-att.s
A llvm/test/MC/X86/avx512dq_vl-att.s
A llvm/test/MC/X86/avx512dq_vl-intel.s
A llvm/test/MC/X86/avx512f_vl-att.s
A llvm/test/MC/X86/avx512f_vl-intel.s
A llvm/test/MC/X86/avx512fp16-att.s
A llvm/test/MC/X86/avx512fp16-intel.s
R llvm/test/MC/X86/avx512fp16.s
A llvm/test/MC/X86/avx512fp16vl-att.s
A llvm/test/MC/X86/avx512fp16vl-intel.s
R llvm/test/MC/X86/avx512fp16vl.s
A llvm/test/MC/X86/avx512gfni-att.s
R llvm/test/MC/X86/avx512gfni-encoding.s
A llvm/test/MC/X86/avx512ifma-att.s
R llvm/test/MC/X86/avx512ifma-encoding.s
A llvm/test/MC/X86/avx512ifmavl-att.s
R llvm/test/MC/X86/avx512ifmavl-encoding.s
A llvm/test/MC/X86/avx512pf-64-att.s
A llvm/test/MC/X86/avx512vaes-att.s
R llvm/test/MC/X86/avx512vaes-encoding.s
A llvm/test/MC/X86/avx512vbmi-att.s
R llvm/test/MC/X86/avx512vbmi-encoding.s
A llvm/test/MC/X86/avx512vbmi-intel.s
A llvm/test/MC/X86/avx512vbmi2-att.s
R llvm/test/MC/X86/avx512vbmi2-encoding.s
A llvm/test/MC/X86/avx512vbmi2vl-att.s
R llvm/test/MC/X86/avx512vbmi2vl-encoding.s
A llvm/test/MC/X86/avx512vbmi_vl-intel.s
A llvm/test/MC/X86/avx512vl-att.s
R llvm/test/MC/X86/avx512vl-encoding.s
A llvm/test/MC/X86/avx512vl_bitalg-att.s
R llvm/test/MC/X86/avx512vl_bitalg-encoding.s
A llvm/test/MC/X86/avx512vl_gfni-att.s
R llvm/test/MC/X86/avx512vl_gfni-encoding.s
A llvm/test/MC/X86/avx512vl_vaes-att.s
R llvm/test/MC/X86/avx512vl_vaes-encoding.s
A llvm/test/MC/X86/avx512vl_vnni-att.s
R llvm/test/MC/X86/avx512vl_vnni-encoding.s
A llvm/test/MC/X86/avx512vnni-att.s
R llvm/test/MC/X86/avx512vnni-encoding.s
A llvm/test/MC/X86/avx512vp2intersect-32-att.s
A llvm/test/MC/X86/avx512vp2intersect-32-intel.s
A llvm/test/MC/X86/avx512vp2intersect-64-att.s
A llvm/test/MC/X86/avx512vp2intersect-64-intel.s
A llvm/test/MC/X86/avx512vp2intersectvl-32-att.s
A llvm/test/MC/X86/avx512vp2intersectvl-32-intel.s
A llvm/test/MC/X86/avx512vp2intersectvl-64-att.s
A llvm/test/MC/X86/avx512vp2intersectvl-64-intel.s
R llvm/test/MC/X86/avx512vp2intersectvl-att.s
R llvm/test/MC/X86/avx512vp2intersectvl-intel.s
A llvm/test/MC/X86/avx512vpopcntdq-64-att.s
A llvm/test/MC/X86/avx_clmul-att.s
A llvm/test/MC/X86/avx_vaes-att.s
R llvm/test/MC/X86/avx_vaes-encoding.s
A llvm/test/MC/X86/avx_vnni-32-intel.s
A llvm/test/MC/X86/avx_vnni-64-att.s
A llvm/test/MC/X86/avx_vnni-64-intel.s
A llvm/test/MC/X86/avx_vnni-att-32.s
R llvm/test/MC/X86/avx_vnni-encoding.s
A llvm/test/MC/X86/bmi-att.s
A llvm/test/MC/X86/cet-att.s
R llvm/test/MC/X86/cet-encoding.s
A llvm/test/MC/X86/fma3-att.s
A llvm/test/MC/X86/fma4-att.s
A llvm/test/MC/X86/gfni-att.s
R llvm/test/MC/X86/gfni-encoding.s
A llvm/test/MC/X86/hle-att.s
R llvm/test/MC/X86/intel-syntax-avx512-error.s
R llvm/test/MC/X86/intel-syntax-avx512.s
R llvm/test/MC/X86/intel-syntax-avx512_bf16.s
R llvm/test/MC/X86/intel-syntax-avx512_bf16_vl.s
R llvm/test/MC/X86/intel-syntax-avx512fp16.s
R llvm/test/MC/X86/intel-syntax-avx512fp16vl.s
R llvm/test/MC/X86/intel-syntax-avx_vnni.s
R llvm/test/MC/X86/intel-syntax-x86-64-avx.s
R llvm/test/MC/X86/intel-syntax-x86-64-avx512_bf16.s
R llvm/test/MC/X86/intel-syntax-x86-64-avx512_bf16_vl.s
R llvm/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s
R llvm/test/MC/X86/intel-syntax-x86-64-avx_vnni.s
R llvm/test/MC/X86/intel-syntax-x86-avx512dq_vl.s
R llvm/test/MC/X86/intel-syntax-x86-avx512vbmi_vl.s
A llvm/test/MC/X86/lwp-64-att.s
A llvm/test/MC/X86/lwp-att.s
R llvm/test/MC/X86/lwp-x86_64.s
R llvm/test/MC/X86/lwp.s
A llvm/test/MC/X86/msrlist-64-att.s
A llvm/test/MC/X86/rand-att.s
A llvm/test/MC/X86/raoint-64-att.s
A llvm/test/MC/X86/raoint-64-intel.s
A llvm/test/MC/X86/rtm-att.s
A llvm/test/MC/X86/sse4a-att.s
A llvm/test/MC/X86/tbm-att.s
R llvm/test/MC/X86/x86-32-avx.s
R llvm/test/MC/X86/x86-32-avx512_vp2intersect-intel.s
R llvm/test/MC/X86/x86-32-avx512vp2intersect-att.s
R llvm/test/MC/X86/x86-64-avx512_bf16-encoding.s
R llvm/test/MC/X86/x86-64-avx512_bf16_vl-encoding.s
R llvm/test/MC/X86/x86-64-avx512_vp2intersect-intel.s
R llvm/test/MC/X86/x86-64-avx512bw.s
R llvm/test/MC/X86/x86-64-avx512bw_vl.s
R llvm/test/MC/X86/x86-64-avx512cd.s
R llvm/test/MC/X86/x86-64-avx512cd_vl.s
R llvm/test/MC/X86/x86-64-avx512dq.s
R llvm/test/MC/X86/x86-64-avx512f_vl.s
R llvm/test/MC/X86/x86-64-avx512pf.s
R llvm/test/MC/X86/x86-64-avx512vp2intersect-att.s
R llvm/test/MC/X86/x86-64-avx512vp2intersectvl-att.s
R llvm/test/MC/X86/x86-64-avx512vp2intersectvl-intel.s
R llvm/test/MC/X86/x86-64-avx512vpopcntdq.s
R llvm/test/MC/X86/x86-64-avx_vnni-encoding.s
R llvm/test/MC/X86/x86-64-msrlist.s
R llvm/test/MC/X86/x86-64-rao-int-att.s
R llvm/test/MC/X86/x86-64-rao-int-intel.s
R llvm/test/MC/X86/x86_64-avx-clmul-encoding.s
R llvm/test/MC/X86/x86_64-avx-encoding.s
R llvm/test/MC/X86/x86_64-bmi-encoding.s
R llvm/test/MC/X86/x86_64-fma3-encoding.s
R llvm/test/MC/X86/x86_64-fma4-encoding.s
R llvm/test/MC/X86/x86_64-hle-encoding.s
R llvm/test/MC/X86/x86_64-rand-encoding.s
R llvm/test/MC/X86/x86_64-rtm-encoding.s
R llvm/test/MC/X86/x86_64-sse4a.s
R llvm/test/MC/X86/x86_64-tbm-encoding.s
R llvm/test/MC/X86/x86_64-xop-encoding.s
A llvm/test/MC/X86/xop-att.s
M llvm/test/TableGen/ContextlessPredicates.td
M llvm/test/TableGen/DefaultOpsGlobalISel.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-eraseroot.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-permutations.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
M llvm/test/TableGen/GlobalISelEmitter-PR39045.td
M llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td
M llvm/test/TableGen/GlobalISelEmitter-atomic_store.td
M llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td
M llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td
M llvm/test/TableGen/GlobalISelEmitter-input-discard.td
M llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td
M llvm/test/TableGen/GlobalISelEmitter-multiple-output.td
M llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
M llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td
M llvm/test/TableGen/GlobalISelEmitter-output-discard.td
M llvm/test/TableGen/GlobalISelEmitter-setcc.td
M llvm/test/TableGen/GlobalISelEmitter-zero-reg.td
M llvm/test/TableGen/GlobalISelEmitter.td
M llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td
M llvm/test/TableGen/GlobalISelEmitterFlags.td
M llvm/test/TableGen/GlobalISelEmitterHwModes.td
M llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td
M llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td
M llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td
M llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td
M llvm/test/TableGen/GlobalISelEmitterRegSequence.td
M llvm/test/TableGen/GlobalISelEmitterSubreg.td
M llvm/test/TableGen/GlobalISelEmitterVariadic.td
M llvm/test/TableGen/HasNoUse.td
M llvm/test/TableGen/address-space-patfrags.td
M llvm/test/TableGen/gisel-physreg-input.td
M llvm/test/TableGen/immarg-predicated.td
M llvm/test/TableGen/immarg.td
M llvm/test/TableGen/predicate-patfags.td
M llvm/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll
M llvm/test/Transforms/ConstraintElimination/debug.ll
M llvm/test/Transforms/ConstraintElimination/reproducer-remarks-debug.ll
M llvm/test/Transforms/Coroutines/coro-debug-O2.ll
M llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll
M llvm/test/Transforms/Coroutines/coro-debug-dbg.values-not_used_in_frame.ll
M llvm/test/Transforms/Coroutines/coro-debug-dbg.values.ll
M llvm/test/Transforms/Coroutines/coro-debug-frame-variable.ll
M llvm/test/Transforms/Coroutines/coro-debug-spill-dbg.declare.ll
M llvm/test/Transforms/Coroutines/coro-debug.ll
M llvm/test/Transforms/Coroutines/coro-split-dbg.ll
M llvm/test/Transforms/Coroutines/swift-async-dbg.ll
A llvm/test/Transforms/CorrelatedValuePropagation/cond-using-block-value.ll
M llvm/test/Transforms/ExpandMemCmp/AArch64/memcmp.ll
M llvm/test/Transforms/ExpandMemCmp/X86/bcmp.ll
M llvm/test/Transforms/ExpandMemCmp/X86/memcmp-x32.ll
M llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll
M llvm/test/Transforms/IndirectBrExpand/basic.ll
M llvm/test/Transforms/InstCombine/div.ll
A llvm/test/Transforms/LICM/variant-aainfo.ll
M llvm/test/Transforms/Util/trivial-auto-var-init-call.ll
M llvm/test/Transforms/Util/trivial-auto-var-init-store.ll
A llvm/test/tools/llvm-objdump/XCOFF/disassemble-abs.test
M llvm/test/tools/llvm-readobj/ELF/AArch64/aarch64-note-gnu-property.s
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/tools/llvm-exegesis/lib/Error.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/llvm-readobj/ObjDumper.cpp
M llvm/tools/obj2yaml/macho2yaml.cpp
M llvm/tools/opt/opt.cpp
M llvm/unittests/Support/CMakeLists.txt
M llvm/unittests/Support/RISCVISAInfoTest.cpp
A llvm/unittests/Support/raw_socket_stream_test.cpp
M llvm/utils/TableGen/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/GlobalISelMatchTable.h
M llvm/utils/TableGen/GlobalISelMatchTableExecutorEmitter.cpp
M llvm/utils/TableGen/README.md
M llvm/utils/count/CMakeLists.txt
M llvm/utils/count/count.c
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
M mlir/include/mlir/Analysis/Presburger/Matrix.h
M mlir/include/mlir/Analysis/Presburger/Utils.h
M mlir/include/mlir/Dialect/ArmSME/Transforms/CMakeLists.txt
M mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/Math/IR/MathOps.td
M mlir/lib/Analysis/Presburger/IntegerRelation.cpp
M mlir/lib/Analysis/Presburger/Matrix.cpp
M mlir/lib/Analysis/Presburger/Utils.cpp
M mlir/lib/Conversion/MathToLibm/MathToLibm.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMInlining.cpp
M mlir/lib/Dialect/Math/IR/MathOps.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/lib/Transforms/Utils/FoldUtils.cpp
M mlir/test/Conversion/MathToLibm/convert-to-libm.mlir
M mlir/test/Dialect/ArmSME/enable-arm-streaming.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-read-2d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-write-2d.mlir
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/Import/global-variables.ll
M mlir/test/Target/LLVMIR/llvmir-debug.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/unittests/Analysis/Presburger/IntegerRelationTest.cpp
M mlir/unittests/Analysis/Presburger/MatrixTest.cpp
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/ff467df0d78d...7b95f93b998a
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