[all-commits] [llvm/llvm-project] dc5570: [RISCV] Update the interface of sifive vqmaccqoq (...

Brandon Wu via All-commits all-commits at lists.llvm.org
Mon Dec 11 21:18:00 PST 2023


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dc5570319676c14c48440b4ee87c8cfb35102ff6
      https://github.com/llvm/llvm-project/commit/dc5570319676c14c48440b4ee87c8cfb35102ff6
  Author: Brandon Wu <brandon.wu at sifive.com>
  Date:   2023-12-12 (Tue, 12 Dec 2023)

  Changed paths:
    M clang/include/clang/Basic/riscv_sifive_vector.td
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmacc_4x8x4.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccu_4x8x4.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vqmaccus_4x8x4.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmacc_4x8x4.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccu_4x8x4.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vqmaccus_4x8x4.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmacc_4x8x4.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccsu_4x8x4.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccu_4x8x4.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vqmaccus_4x8x4.c
    M clang/test/Sema/rvv-required-features.c
    M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
    M llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll

  Log Message:
  -----------
  [RISCV] Update the interface of sifive vqmaccqoq (#74284)

The
spec(https://sifive.cdn.prismic.io/sifive/60d5a660-3af0-49a3-a904-d2bbb1a21517_int8-matmul-spec.pdf)
is updated.




More information about the All-commits mailing list