[all-commits] [llvm/llvm-project] 29ee66: [RISCV] Macro-fusion support for veyron-v1 CPU. (#...

[Mikhail Gudim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 29ee66f4a0967e43a035f147c960743c7b640f2f
      https://github.com/llvm/llvm-project/commit/29ee66f4a0967e43a035f147c960743c7b640f2f
  Author: Mikhail Gudim <mgudim at gmail.com>
  Date:   2023-12-11 (Mon, 11 Dec 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVMacroFusion.cpp
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    A llvm/test/CodeGen/RISCV/macro-fusions-veyron-v1.mir

  Log Message:
  -----------
  [RISCV] Macro-fusion support for veyron-v1 CPU. (#70012)

Support was added for the following fusions:
  auipc-addi, slli-srli, ld-add
Some parts of the code became repetative, so small refactoring of
existing lui-addi fusion was done.