[all-commits] [llvm/llvm-project] 64a9b3: [RISCV] Optimize VRELOAD/VSPILL lowering if VLEN i...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 64a9b355fea89ced300e36108d6eb5a4f0fcd93a
      https://github.com/llvm/llvm-project/commit/64a9b355fea89ced300e36108d6eb5a4f0fcd93a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-12-05 (Tue, 05 Dec 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll

  Log Message:
  -----------
  [RISCV] Optimize VRELOAD/VSPILL lowering if VLEN is known. (#74421)

Instead of using VLENB and a shift, load (VLEN/8)*LMUL directly into a
register. We could go further and use ADDI, but that would be more
intrusive to the code structure.

My primary goal is to remove the read of VLENB which might be expensive
if it's not optimized in hardware.