[all-commits] [llvm/llvm-project] e888e8: [ARM][AArch64] Use SelectionDAG::SplitScalar to si...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e888e83fb64679e7869ddcbc7147b6255abf6315
      https://github.com/llvm/llvm-project/commit/e888e83fb64679e7869ddcbc7147b6255abf6315
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-12-05 (Tue, 05 Dec 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp

  Log Message:
  -----------
  [ARM][AArch64] Use SelectionDAG::SplitScalar to simplify some code. (#74411)

We know we're splitting a type in half to two legal values. Instead of
using shift and truncate that need to be legalized, we can use two
ISD::EXTRACT_ELEMENTs.

Spotted while reviewing #67918 for RISC-V which copied this code.