[all-commits] [llvm/llvm-project] 9fa2d7: [clang-format] Indent Verilog case statements with...

[sstwcw via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9fa2d74be415a3e30d811c0acc05c45e1c55759e
      https://github.com/llvm/llvm-project/commit/9fa2d74be415a3e30d811c0acc05c45e1c55759e
  Author: sstwcw <su3e8a96kzlver at posteo.net>
  Date:   2023-11-29 (Wed, 29 Nov 2023)

  Changed paths:
    M clang/lib/Format/ContinuationIndenter.cpp
    M clang/unittests/Format/FormatTestVerilog.cpp

  Log Message:
  -----------
  [clang-format] Indent Verilog case statements with comments (#71353)

If a line contains a comment outside of (fake) parentheses, the part
following it is indented according to `CurrentState.Indent`. A Verilog
case label and the statement that follows are broken with
mustBreakBefore. So the part that follows the case label needs some
special handling. Previously, that variable was left out. So the
indentation was wrong when there was a comment.

old:

```Verilog
case (data)
  16'd0:
    result = //
        10'b0111111111;
endcase
case (data)
  16'd0:
    //

  //
  result = //
  10'b0111111111;
endcase
```

new:

```Verilog
case (data)
  16'd0:
    result = //
        10'b0111111111;
endcase
case (data)
  16'd0:
    //

    //
    result = //
        10'b0111111111;
endcase
```