[all-commits] [llvm/llvm-project] 3af82b: [clang-format] Add spaces around the Verilog impli...

[sstwcw via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3af82b3962c443d43edba1abb50a82fb3048999a
      https://github.com/llvm/llvm-project/commit/3af82b3962c443d43edba1abb50a82fb3048999a
  Author: sstwcw <su3e8a96kzlver at posteo.net>
  Date:   2023-11-29 (Wed, 29 Nov 2023)

  Changed paths:
    M clang/lib/Format/FormatTokenLexer.cpp
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/unittests/Format/FormatTestVerilog.cpp
    M clang/unittests/Format/TokenAnnotatorTest.cpp

  Log Message:
  -----------
  [clang-format] Add spaces around the Verilog implication operator (#71352)

The Verilog implication operator `->` is a binary operator meaning
either the left hand side is false or the right hand side is true.
Previously it was treated as the C++ struct member operator.

I didn't even know it existed when I added the operator formatting part.
And I didn't check all the tests for all the operators I added. That is
how the bad test got in.