[all-commits] [llvm/llvm-project] d9962c: [IR] Add disjoint flag for Or instructions. (#72583)

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d9962c400f970d17396e84c1a55cdbea29a7c893
      https://github.com/llvm/llvm-project/commit/d9962c400f970d17396e84c1a55cdbea29a7c893
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-24 (Fri, 24 Nov 2023)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/include/llvm/AsmParser/LLToken.h
    M llvm/include/llvm/Bitcode/LLVMBitCodes.h
    M llvm/include/llvm/IR/InstrTypes.h
    M llvm/lib/AsmParser/LLLexer.cpp
    M llvm/lib/AsmParser/LLParser.cpp
    M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
    M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
    M llvm/lib/IR/AsmWriter.cpp
    M llvm/lib/IR/Instruction.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    M llvm/test/Assembler/flags.ll
    M llvm/test/Bitcode/compatibility.ll
    M llvm/test/Bitcode/flags.ll
    M llvm/test/Transforms/InstCombine/freeze.ll
    M llvm/test/Transforms/InstCombine/or.ll
    M llvm/test/Transforms/SimplifyCFG/HoistCode.ll

  Log Message:
  -----------
  [IR] Add disjoint flag for Or instructions. (#72583)

This flag indicates that every bit is known to be zero in at least one
of the inputs. This allows the Or to be treated as an Add since there is
no possibility of a carry from any bit.

If the flag is present and this property does not hold, the result is
poison.

This makes it easier to reverse the InstCombine transform that turns Add
into Or.

This is inspired by a comment here
https://github.com/llvm/llvm-project/pull/71955#discussion_r1391614578

Discourse thread
https://discourse.llvm.org/t/rfc-add-or-disjoint-flag/75036