[all-commits] [llvm/llvm-project] 915e09: [RISCV] Select zext as sext when sign bit is 0 for...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 915e092400f92a617a4ca7cb9f03a642bb30c7cc
      https://github.com/llvm/llvm-project/commit/915e092400f92a617a4ca7cb9f03a642bb30c7cc
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-13 (Mon, 13 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbkb.ll

  Log Message:
  -----------
  [RISCV] Select zext as sext when sign bit is 0 for -riscv-experimental-rv64-legal-i32

In our default SelectionDAG where i32 isn't legal, the zext will become
and i64 AND and often get optimized out on its own. With i32 legal, we
need to turn it in into sext.w and rely on RISCVOptWInstrs to remove it.