[all-commits] [llvm/llvm-project] 647c49: [RISCV] Add an add.uw pattern using zext for -risc...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 647c490f8a994e9632f990d6bdf23d40fc0ffeb3
      https://github.com/llvm/llvm-project/commit/647c490f8a994e9632f990d6bdf23d40fc0ffeb3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-10 (Fri, 10 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll

  Log Message:
  -----------
  [RISCV] Add an add.uw pattern using zext for -riscv-experimental-rv64-legal-i32 and global isel