[all-commits] [llvm/llvm-project] 83cc24: [RISCV] Add test case showing unnecessary zext of ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 83cc24e598b7a6c24bf82a00784429822e636d99
      https://github.com/llvm/llvm-project/commit/83cc24e598b7a6c24bf82a00784429822e636d99
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-10 (Fri, 10 Nov 2023)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/alu32.ll

  Log Message:
  -----------
  [RISCV] Add test case showing unnecessary zext of shift amounts with -riscv-experimental-rv64-legal-i32. NFC


  Commit: a93dfb589d17245aa43d76df8e0835b019e04b7a
      https://github.com/llvm/llvm-project/commit/a93dfb589d17245aa43d76df8e0835b019e04b7a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-10 (Fri, 10 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/alu32.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll

  Log Message:
  -----------
  [RISCV] Peek through zext in selectShiftMask.

This improves the code for -riscv-experimental-rv64-legal-i32


Compare: https://github.com/llvm/llvm-project/compare/309596f24977...a93dfb589d17