[all-commits] [llvm/llvm-project] 7dc20a: [AArch64] Fix spillfill-sve.mir with expensive che...

[Sander de Smalen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7dc20abed0d121b7492b3da261aca9d9ea4d0ad1
      https://github.com/llvm/llvm-project/commit/7dc20abed0d121b7492b3da261aca9d9ea4d0ad1
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2023-11-01 (Wed, 01 Nov 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/test/CodeGen/AArch64/spillfill-sve.mir

  Log Message:
  -----------
  [AArch64] Fix spillfill-sve.mir with expensive checks.

This fixes an issue introduced by PR #70679.

Using constrainRegClass() is not strong enough to actually force
the use of a register to be a PPR register class. It will need an
actual COPY to do the conversion.

The downside is that this introduces an extra register, which is an
issue we may want to fix at a later point using a custom copy operation
where the register allocator uses the same register when it can.