[all-commits] [llvm/llvm-project] d96529: [DAG] Attempt shl narrowing in SimplifyDemandedBit...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d96529af3c362c53ef2e8c883a9e571fb3626927
      https://github.com/llvm/llvm-project/commit/d96529af3c362c53ef2e8c883a9e571fb3626927
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-10-29 (Sun, 29 Oct 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
    M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
    M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
    M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
    M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
    M llvm/test/CodeGen/AMDGPU/xnor.ll
    M llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll
    M llvm/test/CodeGen/X86/atomic-rm-bit-test-64.ll
    M llvm/test/CodeGen/X86/avx512vnni-combine.ll
    M llvm/test/CodeGen/X86/avxvnni-combine.ll
    M llvm/test/CodeGen/X86/bswap.ll
    M llvm/test/CodeGen/X86/buildvec-insertvec.ll
    M llvm/test/CodeGen/X86/cmp-concat.ll
    M llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness-reduced.ll
    M llvm/test/CodeGen/X86/combine-bitreverse.ll
    M llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
    M llvm/test/CodeGen/X86/dagcombine-shifts.ll
    M llvm/test/CodeGen/X86/divmod128.ll
    M llvm/test/CodeGen/X86/extract-bits.ll
    M llvm/test/CodeGen/X86/fold-and-shift.ll
    M llvm/test/CodeGen/X86/fp128-i128.ll
    M llvm/test/CodeGen/X86/lea-dagdag.ll
    M llvm/test/CodeGen/X86/lea-opt2.ll
    M llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
    M llvm/test/CodeGen/X86/parity.ll
    M llvm/test/CodeGen/X86/pr62653.ll
    M llvm/test/CodeGen/X86/select.ll
    M llvm/test/CodeGen/X86/select_const.ll
    M llvm/test/CodeGen/X86/selectcc-to-shiftand.ll
    M llvm/test/CodeGen/X86/setcc.ll
    M llvm/test/CodeGen/X86/shift-combine.ll
    M llvm/test/CodeGen/X86/vector-shuffle-variable-128.ll
    M llvm/test/CodeGen/X86/vector-shuffle-variable-256.ll
    M llvm/test/CodeGen/X86/vselect.ll
    M llvm/test/CodeGen/X86/zext-shl.ll

  Log Message:
  -----------
  [DAG] Attempt shl narrowing in SimplifyDemandedBits (REAPPLIED)

If a shl node leaves the upper half bits zero / undemanded, then see if we can profitably perform this with a half-width shl and a free trunc/zext.

Followup to D146121

Reapplied - moved after the ShrinkDemandedOp call; reuse the existing KnownBits result; ensure that we only attempt this if all the upper bits are demanded; 547dc461225ba should address the remaining regressions that were noticed in the previous commit.

Differential Revision: https://reviews.llvm.org/D155472