[all-commits] [llvm/llvm-project] f9cd78: [AMDGPU] Add pseudo instructions for SGPR spill to...

[Christudasan Devadasan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f9cd7896581a56494fd2d07d5126e614de7d57d2
      https://github.com/llvm/llvm-project/commit/f9cd7896581a56494fd2d07d5126e614de7d57d2
  Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
  Date:   2023-10-27 (Fri, 27 Oct 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
    M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
    M llvm/test/CodeGen/AMDGPU/extend-wwm-virt-reg-liveness.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir
    M llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
    M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
    M llvm/test/CodeGen/AMDGPU/spill192.mir
    M llvm/test/CodeGen/AMDGPU/spill224.mir
    M llvm/test/CodeGen/AMDGPU/spill288.mir
    M llvm/test/CodeGen/AMDGPU/spill320.mir
    M llvm/test/CodeGen/AMDGPU/spill352.mir
    M llvm/test/CodeGen/AMDGPU/spill384.mir
    M llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir
    M llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir
    M llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir

  Log Message:
  -----------
  [AMDGPU] Add pseudo instructions for SGPR spill to VGPR (#69923)

For a future patch, is it important to keep the lowered SGPR
spills to be recognized as spill instructions during regalloc.
Directly lowering them into V_WRITELANE/V_READLANE won't allow
us to attach the SPILL flag to their instructions.

This patch introduces the pseudo instructions with the SGPRSpill
flag set in their Desc. They will get lowered to equivalent
instructions later during post RA pseudo expansion.