[all-commits] [llvm/llvm-project] d307dc: [RISCV][GISel] Allow G_AND/G_OR/G_XOR to have s32 ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d307dc5b512753efa4db45576fa9aeed1de97e62
      https://github.com/llvm/llvm-project/commit/d307dc5b512753efa4db45576fa9aeed1de97e62
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-10-26 (Thu, 26 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-abs.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-addo-subo.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-and.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ashr.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-div.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-load.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-lshr.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-or.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-rem.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-shl.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-store.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-xor.mir

  Log Message:
  -----------
  [RISCV][GISel] Allow G_AND/G_OR/G_XOR to have s32 types on RV64.

Even though we don't have W instructions for them. This treats them
the same as other binary operators.