[all-commits] [llvm/llvm-project] 78941e: [llvm][AArch64][Assembly]: Add FP8 instructions as...

[hassnaaHamdi via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 78941e1eedb121344e0d969458ea85598cd749df
      https://github.com/llvm/llvm-project/commit/78941e1eedb121344e0d969458ea85598cd749df
  Author: hassnaaHamdi <hassnaa.hamdi at arm.com>
  Date:   2023-10-26 (Thu, 26 Oct 2023)

  Changed paths:
    M llvm/include/llvm/TargetParser/AArch64TargetParser.h
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/MC/AArch64/FP8/directive-arch-negative.s
    A llvm/test/MC/AArch64/FP8/directive-arch.s
    A llvm/test/MC/AArch64/FP8/miscellaneous-fp8-diagnostics.s
    A llvm/test/MC/AArch64/FP8/miscellaneous-fp8.s
    A llvm/test/MC/AArch64/FP8_SME2/cvt-diagnostics.s
    A llvm/test/MC/AArch64/FP8_SME2/cvt.s
    A llvm/test/MC/AArch64/FP8_SME2/fscale-diagnostics.c
    A llvm/test/MC/AArch64/FP8_SME2/fscale.s
    A llvm/test/MC/AArch64/FP8_SVE2/fcvt-diagnostics.s
    A llvm/test/MC/AArch64/FP8_SVE2/fcvt.s
    A llvm/test/MC/AArch64/FP8_SVE2/fcvtn-diagnostics.s
    A llvm/test/MC/AArch64/FP8_SVE2/fcvtn.s
    M llvm/test/MC/AArch64/SVE2/fcvtnt-diagnostics.s
    M llvm/unittests/TargetParser/TargetParserTest.cpp

  Log Message:
  -----------
  [llvm][AArch64][Assembly]: Add FP8 instructions assembly and disassembly. (#69632)

This patch adds the feature flag FP8 and the assembly/disassembly
for the following instructions of NEON, SVE2 and SME2:
  * NEON Instructions:
    + Advanced SIMD two-register miscellaneous:
      - F1CVTL, F1CVTL2, F2CVTL, F2CVTL2 
      - BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2
    + Advanced SIMD three-register extension:
       - FCVTN, FCVTN2 (FP32 to FP8) 
       - FCVTN (FP16 to FP8)
    + Advanced SIMD three same:
      - FSCALE
  * SVE2 Instructions:
    + Downconvert instructions:
       - FCVTN_Z2Z_HtoB
       - FCVTNB_Z2Z_StoB 
       - BFCVTN_Z2Z_HtoB 
       - FCVTNT_Z2Z_StoB
     + Upconvert instructions:
          - F1CVT_ZZ, F2CVT_ZZ
          - BF1CVT_ZZ, BF2CVT_ZZ
          - F1CVTLT_ZZ, F2CVTLT_ZZ 
          - BF1CVTLT_ZZ, BF2CVTLT_ZZ

  * SME2 Instructions:
    - F1CVT_2ZZ, F2CVT_2ZZ
    - BF1CVT_2ZZ, BF2CVT_2ZZ
    - F1CVTL_2ZZ, F2CVTL_2ZZ
    - BF1CVTL_2ZZ, BF2CVTL_2ZZ
    - FCVT_Z2Z_HtoB, BFCVT_Z2Z_HtoB
    - FCVT_Z4Z - FCVTN_Z4Z
    - FSCALE_2ZZ, FSCALE_4ZZ
    - FSCALE_2Z2Z, FSCALE_4Z4Z

That is according to this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09