[all-commits] [llvm/llvm-project] b47ff3: [InstCombine] Drop exact flag instead of increasin...

[Nikita Popov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b47ff361345a02e783452fdfb03eab3a7718758e
      https://github.com/llvm/llvm-project/commit/b47ff361345a02e783452fdfb03eab3a7718758e
  Author: Nikita Popov <npopov at redhat.com>
  Date:   2023-10-26 (Thu, 26 Oct 2023)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    M llvm/test/Transforms/InstCombine/cast.ll
    M llvm/test/Transforms/InstCombine/select-2.ll
    M llvm/test/Transforms/InstCombine/shift.ll

  Log Message:
  -----------
  [InstCombine] Drop exact flag instead of increasing demanded bits (#70311)

Demanded bit simplification for lshr/ashr will currently demand the low
bits if the exact flag is set. This is because these bits must be zero
to satisfy the flag.

However, this means that our demanded bits simplification is worse for
lshr/ashr exact than it is for plain lshr/ashr, which is generally not
desirable.

Instead, drop the exact flag if a demanded bits simplification of the
operand succeeds, which may no longer satisfy the exact flag.

This matches what we do for the exact flag on udiv, as well as the
nuw/nsw flags on add/sub/mul.