[all-commits] [llvm/llvm-project] 12dfcc: [DAG] Update test case for Issue #69965

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 12dfcc02388810e113cca359b2b529c98d02307c
      https://github.com/llvm/llvm-project/commit/12dfcc02388810e113cca359b2b529c98d02307c
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-10-26 (Thu, 26 Oct 2023)

  Changed paths:
    M llvm/test/CodeGen/X86/pr69965.ll

  Log Message:
  -----------
  [DAG] Update test case for Issue #69965

The previous reduced test case just showed a minor codegen regression, this test now shows the actual miscompilation


  Commit: 547dc461225ba65b6d5dac34efd31d2c8c5b1049
      https://github.com/llvm/llvm-project/commit/547dc461225ba65b6d5dac34efd31d2c8c5b1049
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-10-26 (Thu, 26 Oct 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/X86/pr69965.ll

  Log Message:
  -----------
  [DAG] SimplifyDemandedBits - ensure we drop NSW/NUW flags when we simplify a SHL node's input

We already do this for variable shifts, but we missed it for constant shifts

Fixes #69965


Compare: https://github.com/llvm/llvm-project/compare/ba3d6e049923...547dc461225b