[all-commits] [llvm/llvm-project] f7dc26: [mlir] Fixed typo in type (128x64 -> 64x128) in TM...

[Guray Ozen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f7dc26cab25e1000b1198625e30ce1acdbe8fcb4
      https://github.com/llvm/llvm-project/commit/f7dc26cab25e1000b1198625e30ce1acdbe8fcb4
  Author: Guray Ozen <guray.ozen at gmail.com>
  Date:   2023-10-26 (Thu, 26 Oct 2023)

  Changed paths:
    M mlir/test/Integration/GPU/CUDA/sm90/tma_load_64x64_swizzle128b.mlir

  Log Message:
  -----------
  [mlir] Fixed typo in type (128x64 -> 64x128) in TMA load test (#70022)

The test was meant to check `64x128xf16` as the contiguous dimension
exceeds the cache line (128b). TMA requires cache line-aligned loads, so
loading 64x128 can be done with two 64x64 loads, as documented in the
test.

However, there was a typo in the type, which was `memref<128x64xf16>`
instead of the correct `memref<64x128xf16>`. This PR corrects the issue
and updates the verification.