[all-commits] [llvm/llvm-project] 18775a: [AArch64][SVE2] Use rshrnb for masked stores (#70026)

[Matthew Devereau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 18775a49416cf767b34eaaf925df5143e40582f4
      https://github.com/llvm/llvm-project/commit/18775a49416cf767b34eaaf925df5143e40582f4
  Author: Matthew Devereau <matthew.devereau at arm.com>
  Date:   2023-10-26 (Thu, 26 Oct 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-combine-rshrnb.ll

  Log Message:
  -----------
  [AArch64][SVE2] Use rshrnb for masked stores (#70026)

This patch is a follow up on https://reviews.llvm.org/D155299. This
patch combines add+lsr to rshrnb when 'B' in:

  C = A + B
  D = C >> Shift

is equal to (1 << (Shift-1), and the bits in the top half of each vector
element are zeroed or ignored, such as in a truncating masked store.