[all-commits] [llvm/llvm-project] 109aa5: [RISCV] Add an experimental pseudoinstruction to r...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 109aa586f073d27120b6c07afe673f30f58d9879
      https://github.com/llvm/llvm-project/commit/109aa586f073d27120b6c07afe673f30f58d9879
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-10-25 (Wed, 25 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/CMakeLists.txt
    M llvm/lib/Target/RISCV/RISCV.h
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O0-pipeline.ll
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/imm.ll
    A llvm/test/CodeGen/RISCV/pr69586.ll

  Log Message:
  -----------
  [RISCV] Add an experimental pseudoinstruction to represent a rematerializable constant materialization sequence. (#69983)

Rematerialization during register allocation is currently limited to a
single instruction with no inputs.

This patch introduces a pseudoinstruction that represents the
materialization of a constant. I've started with a sequence of 2
instructions for now, which covers at least the common LUI+ADDI(W) case.
This instruction will be expanded into real instructions immediately
after register allocation using a new pass. This gives the post-RA
scheduler a chance to separate the 2 instructions to improve ILP.

I believe this matches the approach used by AArch64.

Unfortunately, this loses some CSE opportunies when an LUI value is used
by multiple constants with different LSBs.

This feature is off by default and a new backend command line option is
added to enable it for testing.

This avoids the spill and reloads reported in #69586.