[all-commits] [llvm/llvm-project] 674b53: [RISCV][GISel] Add widenScalarToNextPow2 to G_SEXT...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 674b53d1a429373b77e7a3ead00b961fa2018ab9
      https://github.com/llvm/llvm-project/commit/674b53d1a429373b77e7a3ead00b961fa2018ab9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-10-25 (Wed, 25 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-extload.mir

  Log Message:
  -----------
  [RISCV][GISel] Add widenScalarToNextPow2 to G_SEXTLOAD/G_ZEXTLOAD legalization.

This fixes i8->i48 on RV64.