[all-commits] [llvm/llvm-project] 8efd67: [RISCV][GISel] Add clampScalar G_ZEXTLOAD/G_SEXTLO...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8efd6799f006000a5e3aacbb403f262db37290b6
      https://github.com/llvm/llvm-project/commit/8efd6799f006000a5e3aacbb403f262db37290b6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-10-25 (Wed, 25 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-extload.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-extload.mir

  Log Message:
  -----------
  [RISCV][GISel] Add clampScalar G_ZEXTLOAD/G_SEXTLOAD legalization rules.

This fixes i8->i16 on RV32/RV64 and i8/i16/i32->i64 on RV64.