[all-commits] [llvm/llvm-project] 34af57: [RISCV][GISel] Add G_SEXTLOAD to legalizer and reg...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 34af57c5c170f80e3ad0dfb469bf7fcc99c2e1af
      https://github.com/llvm/llvm-project/commit/34af57c5c170f80e3ad0dfb469bf7fcc99c2e1af
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-10-25 (Wed, 25 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-extload.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-extload.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir

  Log Message:
  -----------
  [RISCV][GISel] Add G_SEXTLOAD to legalizer and regbank select. Add instruction selection tests.

This updates our G_SEXTLOAD support to the same level as G_ZEXTLOAD.
Still missing some legalizer rules for both though.