[all-commits] [llvm/llvm-project] b2accb: [RISCV] Mark V0 regclasses as larger superclasses ...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b2accb9d8e597bc656fac0d64b242471ef8ca6e6
      https://github.com/llvm/llvm-project/commit/b2accb9d8e597bc656fac0d64b242471ef8ca6e6
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-10-24 (Tue, 24 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll

  Log Message:
  -----------
  [RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)