[all-commits] [llvm/llvm-project] 20020c: [DAGCombiner] Fix misuse of getZeroExtendInReg in ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 20020c1b43d543034dcc4a0c1715db558d6de773
      https://github.com/llvm/llvm-project/commit/20020c1b43d543034dcc4a0c1715db558d6de773
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-10-24 (Tue, 24 Oct 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  Log Message:
  -----------
  [DAGCombiner] Fix misuse of getZeroExtendInReg in SimplifySelectCC. (#70066)

If VT has less bits than SCC, using a ZeroExtendInReg isn't going to fix
it. That's an AND instruction. We need to truncate the value instead.

This should be ok because we already checked that the boolean contents
is ZeroOrOne so the setcc can only produce 0 or 1.

No test because I found this while trying to make i32 legal for RISC-V
64 which I'm not ready to upload yet. You can see in the coverage report
that this line isn't tested today.


https://lab.llvm.org/coverage/coverage-reports/coverage/Users/buildslave/jenkins/workspace/coverage/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp.html#L27270