[all-commits] [llvm/llvm-project] 51446d: [RISCV] Only check for scalar VT at depth 0 in has...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 51446d945adb0ffdbfde4dc85396540c1c650638
      https://github.com/llvm/llvm-project/commit/51446d945adb0ffdbfde4dc85396540c1c650638
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-10-23 (Mon, 23 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

  Log Message:
  -----------
  [RISCV] Only check for scalar VT at depth 0 in hasAllNBitUsers.

VTs on already selected instructions can be arbitrary. Reviewing
the isel table I see i32 used for instructions that are part of
multiple instruction output patterns. Looks like tblgen to just
picks the lowest numbered MVT that is legal for the destination
register class of the instruction.

Seems better to just not check types for already selected nodes.