[all-commits] [llvm/llvm-project] 725278: RegAllocGreedy: Fix detection of lanes read by a b...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7252787dd95d3423c5160c11ad4cb89b3c5cd8f5
      https://github.com/llvm/llvm-project/commit/7252787dd95d3423c5160c11ad4cb89b3c5cd8f5
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-10-01 (Sun, 01 Oct 2023)

  Changed paths:
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
    M llvm/test/CodeGen/Thumb2/mve-vst3.ll

  Log Message:
  -----------
  RegAllocGreedy: Fix detection of lanes read by a bundle

SplitKit creates questionably formed bundles of copies
when it needs to copy a subset of live lanes and can't do
it with a single subregister index. These are merely marked
as part of a bundle, and don't start with a BUNDLE instruction.
Queries for the slot index would give the first copy in the
bundle, and we need to inspect the operands of all the other
bundled copies.

Also fix and simplify detection of read lane subsets. This causes
some RISCV test regressions, but these look like accidentally beneficial
splits. I don't see a subrange based reason to perform these splits.

Avoids some really ugly regressions in a future patch.

https://reviews.llvm.org/D146859


  Commit: d8127b2ba8a87a610851b9a462f2fc2526c36e37
      https://github.com/llvm/llvm-project/commit/d8127b2ba8a87a610851b9a462f2fc2526c36e37
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-10-01 (Sun, 01 Oct 2023)

  Changed paths:
    M llvm/lib/CodeGen/InlineSpiller.cpp
    M llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/AMDGPU/swdev380865.ll
    M llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
    M llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
    M llvm/test/CodeGen/Thumb2/mve-vst3.ll

  Log Message:
  -----------
  InlineSpiller: Consider if all subranges are the same when avoiding redundant spills

This avoids some redundant spills of subranges, and avoids a compile failure.
This greatly reduces the numbers of spills in a loop.

The main range is not informative when multiple instructions are needed to fully define
a register. A common scenario is a lowered reg_sequence where every subregister
is sequentially defined, but each def changes the main range's value number. If
we look at specific lanes at the use index, we can see the value is actually the
same.

In this testcase, there are a large number of materialized 64-bit constant defs
which are hoisted outside of the loop by MachineLICM. These are feeding REG_SEQUENCES,
which is not considered rematerializable inside the loop. After coalescing, the split
constant defs produce main ranges with an apparent phi def. There's no phi def if you look
at each individual subrange, and only half of the register is really redefined to a constant.

Fixes: SWDEV-380865

https://reviews.llvm.org/D147079


Compare: https://github.com/llvm/llvm-project/compare/5b7a7ec5a210...d8127b2ba8a8