[all-commits] [llvm/llvm-project] b28d83: [RISCV][MC] Recognise that fcvt.d.s with frm != 0b...

[Alex Bradbury via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b28d83eec44831e1c1dfcb861564a0beb74c7e9b
      https://github.com/llvm/llvm-project/commit/b28d83eec44831e1c1dfcb861564a0beb74c7e9b
  Author: Alex Bradbury <asb at igalia.com>
  Date:   2023-09-30 (Sat, 30 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/test/MC/RISCV/fp-default-rounding-mode.s
    M llvm/test/MC/RISCV/fp-inx-default-rounding-mode.s
    M llvm/test/MC/RISCV/rv32d-valid.s
    M llvm/test/MC/RISCV/rv32zdinx-valid.s

  Log Message:
  -----------
  [RISCV][MC] Recognise that fcvt.d.s with frm != 0b000 is valid (#67555)

This seems to be an issue common to both GCC and LLVM. There are various
RISC-V FCVT instructions where the frm field makes no difference to the
output as the result is always exact (e.g. fcvt.d.s, fcvt.s.h,
fcvt.d.h). As with GCC, we always generate a form of these fcvt
instructions where frm=0b000. However, the ISA manual _doesn't_ state
that frm values are invalid, and we should ensure we can accept them.
This patch does so by adding the frm field to fcvt.d.s and adding an
InstAlias so that if no frm is specified, it defaults to rne (0b000).

This patch just corrects fcvt.d.s in order to allow the approach to be
reviewed, before applying it to the other affected instructions.

I haven't added tests to llvm/test/MC/Disassembler/RISCV, because it
doesn't seem necessary to test there in addition to our usual round-trip
tests in llvm/test/MC/RISCV. But feedback is welcome.

Recently added tests ensure that the default `rne` rounding mode is
printed as desired.