[all-commits] [llvm/llvm-project] f71ad1: [AArch64] Add a target feature for AArch64StorePai...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f71ad19c04763b858e53e0e291698b769b7c2bfc
      https://github.com/llvm/llvm-project/commit/f71ad19c04763b858e53e0e291698b769b7c2bfc
  Author: David Green <david.green at arm.com>
  Date:   2023-09-30 (Sat, 30 Sep 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
    M llvm/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
    M llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll
    M llvm/test/CodeGen/AArch64/arm64-windows-calls.ll
    M llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
    M llvm/test/CodeGen/AArch64/no-sve-no-neon.ll
    M llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll

  Log Message:
  -----------
  [AArch64] Add a target feature for AArch64StorePairSuppress

The AArch64StorePairSuppress pass prevents the creation of STP under some
heuristics. Unfortunately it often prevents the creation of STP in cases where
it is obviously beneficial, and it doesn't match my understanding of
scheduling/cpu pipelining to prevent the creation of STP. From some
benchmarking, even on an in-order cpu where the scheduling is most important I
don't see it giving better results. In general the lower instruction count for
STP would be expected to give a slightly better cycle count.

As the pass specifically mentions the cyclone cpu, this patch adds a target
feature for FeatureStorePairSuppress, enabled for all the non-Arm cpus. This
has the effect of disabling it for all Arm cpus.

Differential Revision: https://reviews.llvm.org/D134646