[all-commits] [llvm/llvm-project] cc9ba5: [test] -march -> -mtriple (#67741)

[Visoiu Mistrih Francis via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cc9ba5600e540fd4e059d20591917962a6df043d
      https://github.com/llvm/llvm-project/commit/cc9ba5600e540fd4e059d20591917962a6df043d
  Author: Visoiu Mistrih Francis <890283+francisvm at users.noreply.github.com>
  Date:   2023-09-29 (Fri, 29 Sep 2023)

  Changed paths:
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
    M llvm/test/CodeGen/RISCV/copy-frameindex.mir
    M llvm/test/CodeGen/RISCV/live-sp.mir
    M llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
    M llvm/test/CodeGen/RISCV/machine-outliner-position.mir
    M llvm/test/CodeGen/RISCV/machineoutliner-jumptable.mir
    M llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir
    M llvm/test/CodeGen/RISCV/machineoutliner.mir
    M llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
    M llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir
    M llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
    M llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
    M llvm/test/CodeGen/RISCV/stack-inst-compress.mir
    M llvm/test/CodeGen/RISCV/stack-slot-coloring.mir
    M llvm/test/CodeGen/RISCV/verify-instr.mir
    M llvm/test/MachineVerifier/test_g_brindirect_is_indirect_branch.mir
    M llvm/test/MachineVerifier/test_g_brjt_is_indirect_branch.mir
    M llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll

  Log Message:
  -----------
  [test] -march -> -mtriple (#67741)

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