[all-commits] [llvm/llvm-project] 6f5b37: [AArch64][SME2][SVE2p1] Add PNR_3b regclass (#67785)

[Matthew Devereau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6f5b372d593f1d08f6569a32f529b6bd5106237c
      https://github.com/llvm/llvm-project/commit/6f5b372d593f1d08f6569a32f529b6bd5106237c
  Author: Matthew Devereau <matthew.devereau at arm.com>
  Date:   2023-09-29 (Fri, 29 Sep 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
    M llvm/test/CodeGen/AArch64/aarch64-sme2-asm.ll
    M llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll
    M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
    M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir

  Log Message:
  -----------
  [AArch64][SME2][SVE2p1] Add PNR_3b regclass (#67785)

This patch adds the PNR_3b regclass for predicate-as-counter registers
0-7 and allows the Upl ASM constraint to use this register class.