[all-commits] [llvm/llvm-project] 2cd244: [AMDGPU] Src1 of VOP3 DPP instructions can be SGPR...

[Mirko Brkušanin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2cd2445c21bc397628cd419817bbaf54224fd21e
      https://github.com/llvm/llvm-project/commit/2cd2445c21bc397628cd419817bbaf54224fd21e
  Author: Mirko Brkušanin <Mirko.Brkusanin at amd.com>
  Date:   2023-09-29 (Fri, 29 Sep 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPU.td
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
    M llvm/lib/Target/AMDGPU/GCNSubtarget.h
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
    M llvm/test/CodeGen/AMDGPU/dpp_combine.ll
    M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
    A llvm/test/MC/AMDGPU/gfx1150_asm_features.s
    M llvm/test/MC/AMDGPU/gfx11_asm_err.s
    A llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_features.txt

  Log Message:
  -----------
  [AMDGPU] Src1 of VOP3 DPP instructions can be SGPR on supported subtargets (#67461)

In order to avoid duplicating every dpp pseudo opcode that has src1, we
allow it for all opcodes and add manual checks on subtargets that do not
support it.