[all-commits] [llvm/llvm-project] 0d328e: [AArch64][SME] Use PNR Reg classes for predicate c...

[Matthew Devereau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0d328e3875285e8b0163b536aef747e0deba5261
      https://github.com/llvm/llvm-project/commit/0d328e3875285e8b0163b536aef747e0deba5261
  Author: Matthew Devereau <matthew.devereau at arm.com>
  Date:   2023-09-29 (Fri, 29 Sep 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/aarch64-sme2-asm.ll

  Log Message:
  -----------
  [AArch64][SME] Use PNR Reg classes for predicate constraint (#67606)

This patch fixes an error where ASM with constraints cannot select SME
instructions which use the top eight predicate-as-counter registers.