[all-commits] [llvm/llvm-project] 7cc83c: [AArch64] Don't expand RSHRN intrinsics to add+srl...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7cc83c5a18b5312c56fd01fe0dce6a9bcd0f856f
      https://github.com/llvm/llvm-project/commit/7cc83c5a18b5312c56fd01fe0dce6a9bcd0f856f
  Author: David Green <david.green at arm.com>
  Date:   2023-09-29 (Fri, 29 Sep 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-vshift.ll

  Log Message:
  -----------
  [AArch64] Don't expand RSHRN intrinsics to add+srl+trunc.

We expand aarch64_neon_rshrn intrinsics to trunc(srl(add)), having tablegen
patterns to combine the results back into rshrn. See D140297.  Unfortunately,
but perhaps not surprisingly, other combines can happen that prevent us
converting back.  For example sext(rshrn) becomes sext(trunc(srl(add))) which
will turn into sext_inreg(srl(add))).

This patch just prevents the expansion of rshrn intrinsics, reinstating the old
tablegen patterns for selecting them. This should allow us to still regognize
the rshrn instructions from trunc+shift+add, without performing any negative
optimizations for the intrinsics.

Closes #67451